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Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these performances.In this article, we will detail how to assess rigorously power consumption, area, speed, code density and processing power for an embedded MCU. For each performance, we will describe how the parameters have to be selected to enable a fair comparison between processor cores.

In traditional short-haul microwave transmission (that is, line-of-sight microwave transmissions operating in the 18 GHz and 23 GHz radio bands),RF design engineers typically are concerned with signal aspects such as fade margins, signal reflections, multipath signals, and so forth. Like an accountant seeking to balance a financial spreadsheet, an RF design engineer normally creates an RF budget table, expressed in decibels (dB), in order to establish a wireless design. Aspects like transmit power and antenna gain are registered in the assets (or plus) column, and free space attenuation, antenna alignment, and atmospheric losses are noted in the liabilities (or minus) column. The goal is to achieve a positive net signal strength adequate to support the wireless path(s) called for in the design.

TTE Systems' RapidiTTy IDE provides a self-contained environment for developers who wish to create "time-triggered" microcontroller software in order to improve overall system reliability. RapidiTTy (Figure 1, below) is intended to address deeply-embedded applications including control and monitoring operations in medical, defence, automotive and industrial sectors, as well as in white and brown goods.

Imagine that a guest is about to depart from your house. She (or he) pauses to check her appearance in an antique-looking mirror mounted near the front door. Suddenly, the image of your guest undergoes a Matrix-like 'ripple' and is replaced with a strange face saying… …actually, we'll move on to consider what the face might say in a moment, but first let me introduce you to a few underlying concepts. Just a few days ago as I pen these words, I came across about a very cool website that describes a really cunning idea called a Magic Mirror (http://diymagicmirror.com).

This article features an example chapter from a new *Hot-off-the-Press* book on FPGA Design that just recently hit the streets in August 2010. This chapter is reproduced here with the kind permission of the publisher – Springer. This book -- FPGA Design: Best Practices for Team-Based Design -- describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed.

Power and energy are key design considerations across a spectrum of computing solutions, from supercomputers and data centers to handheld phones and other mobile computers. A large body of work focuses on managing power and improving energy efficiency. While prior work is easily summarized in two words—"Avoid waste!"—the challenge is figuring out where and why waste happens and determining how to avoid it. In this article, I discuss how, at a general level, many inefficiencies, or waste, stem from the inherent way system architects address the complex trade-offs in the system-design process. I discuss common design practices that lead to power inefficiencies in typical systems and provide an intuitive categorization of high-level approaches to addressing them. The goal is to provide practitioners—whether in systems, packaging, algorithms, user interfaces, or databases—a set of tools, or "recipes," to systematically reason about and optimize power in their respective domains.