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At three separate industry events last week, engineers said they are gearing up to deliver in 2011 chips that can handle serial data streams running at 25 Gbits/second to drive next-generation 100 and 400 Gbit/second networks. But they say it's still a mystery how—or if—they can deliver follow-on components for the terabit networks today's Internet data centers are already demanding. The kinds of jobs required to run today's Web 2.0 services such as Google and Facebook can completely overwhelm current 10 Gbit/s Ethernet links in the warehouse-sized data centers those companies use. Such data centers could use hundreds of 100 Gbit/s Ethernet links today, although standards for such networks are still being completed.

During the Google IO event, two new great features of the popular Android OS were announced. The most important from a robotics point of view is the Android Open Accessory standard that is Arduino based and enables Android devices to integrate with hardware via usb (or bluetooth in the near future). You can read more in the posts on engadget.com and robots-dreams.com (where the video is from). Also engadget reports on the Android @ Home framework that aspires to interconnect every home appliance, device or gadget to an integrated network. More information and details will be announced soon from Google but already the potential for various robotic applications that could take advantage of these projects looks promising.

The embedded world is constantly changing. You might not have noticed, but if you take a minute to recall what a microcontroller system was like 10 years ago and compare it to today's latest microcontroller systems, you will find that PCB design, component packages, level of integration, clock speed, and memory size have all going through several generations of change. One of the hottest topics in this area is when will the last of remaining 8-bit microcontroller users start to move away from legacy architectures and move to modern 32-bit processor architectures like the ARM Cortex-M based microcontroller family. Over the last few years there has been a strong momentum of embedded developers starting the migration to 32-bit microcontrollers and, in this multi-part article, we will take a look at some of the factors accelerating this migration.

Ever since graphene was first produced in a lab at the University of Manchester in 2004, researchers around the world have been fascinated with its potential in electronics applications. Graphene possessed all the benefits of carbon nanotubes (CNTs), namely its charged-carrier mobility, but it didn’t have any of the down sides, such as CNTs’ need for different processing techniques than silicon and the intrinsic difficulty of creating interconnects for CNTs. But all was not easy for applying graphene to electronics applications. One of the fundamental problems for graphene was its lack of a band gap, which left it with a very low on-off ratio measured at about 10 as compared to in the 100s for silicon. Now this fundamental hurdle has been overcome. Based on research led by Phaedon Avouris at IBM’s IBM T.J. Watson Research Center, Yorktown Heights, New York, IBM is reporting that they have created a significant band gap in graphene.

The MAX13171E along with the MAX13173E/ MAX13175E, form a complete pin-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that support the V.28 (RS-232), V.10/V.11 (RS-449/V.36, RS-530, RS-530A, X.21), and V.35 protocols. The MAX13171E transceivers carry the high-speed clock and data signals, while the MAX13173E transceivers carry the control signals. The MAX13171E can be terminated by the MAX13175E pin-selectable resistor termination network. The MAX13175E contains six pin-selectable, multiprotocol cable termination networks.

A little more than a week after long-simmering programmable logic startup Tabula Inc. emerged from stealth mode, Tier Logic Inc. stepped into the light Wednesday (March 10), offering the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die. Like Tabula, Tier Logic's technology depends on a three-dimensional structure. But while Tabula uses rapid reconfiguration to, in the words of that firm's executives, treat time as the third dimension, Tier Logic's approach separates user circuits and configuration circuits into 3-D stacked layers, creating what the company calls the world's first monolithic 3-D FPGA.

ON Semiconductor has expanded its multiplexer product line with devices that are designed to function at high input rates/clock frequencies. The NB6VQ572M, NB6LQ572, NB7L572, NB6L572M, NB7LQ572, NB6LQ572M, NB7VQ58M and NB7V58M mux/fanout devices are targeted at SONET, Gigabit Ethernet, Fiber Channel, backplane and other clock/data distribution applications. The NB6VQ572M and NB6LQ572M differential 4:1 clock/data input multiplexers with 1:2 current mode logic (CML) clock/data fanout buffers operate at up to 6 GHz/8 Gbps from a 1.8 V, 2.5 V or 3.3 V power supply. The new devices have a data dependent jitter of <10 ps and random clock jitter of less than 0.8 ps RMS.

Let’s face it. Most of the gear you use at work or play has multicore processors in it. Your laptop has them (the CPU itself has two cores, and the dedicated graphics processor has many more). That game console in the living room has still more, and even a high-end smartphone typically has a CPU and graphics core on a single chip. Out of sight but definitely not out of mind–particularly if they cease working–are the servers and high-throughput network routers, all which have numerous multicore processors in them. The multiple cores in these devices work in concert to provide quick responses to user queries or to manage the smooth flow of data throughout the office.

Synopsys, Inc., has unveiled the DesignWare Ethernet Quality-of-Service (QoS) Controller IP which implements the new IEEE specifications for audio video bridging (AVB) features. The DesignWare Ethernet IP solution supports the new IEEE 802.1AS and 802.1-Qav version D6.0 specifications. These specifications enable efficient networking of streaming audio video (AV) applications through IEEE 802.1 networks found in consumer electronics, automotive AV and professional sound system products. Synopsys' DesignWare Ethernet QoS Controller, which supports 10/100/1G data transfer speeds, allows designers to develop system-on-chips (SoCs) that deliver time-synchronized, low-latency audio and video over Ethernet networks with exceptional quality-of-service while retaining compatibility with legacy networks.

Length-match your traces to within 100 mils. Or is it 10 mils? Or should you go down to 1 mil? Should you include the lengths of the vias? How about the lengths of resistors? Understanding the origin of length-matching requirements, coupled with some rudimentary signal integrity analysis, can help answer these questions.   Determining length requirements requires an understanding of flight time, electrical length vs. physical length, loading and signal quality. Those elements are vital in determining what the length really needs to be, as well as in determining the allowable trade-offs to meet system timing goals.