Group items tagged

In earlier articles on intelligent sensor design, we saw how valuable they can be to both end users and those who manufacture and sell them. It’s now time to delve more deeply into what it takes to make intelligent sensors work.   The first step in that journey is to develop a solid, intuitive understanding of the principles of digital signal processing(DSP). Unlike many introductory DSP articles and texts, the focus here will be on presenting and using the important concepts rather than deriving them, for the simple reason that addressing the subject in depth is a book-sized, not a chapter-sized, project.

Within the next three years, the U.S. military will test the feasibility of sending a quadruped robot out into the field as a trusty pack mule to carry supplies for its troops, wherever they go. If the testing goes well for Boston Dynamics's Legged Squad Support System (LS3), company founder Marc Raibert will have come a long way from the one-legged hopping robots he pioneered in the 1980s. Actually Raibert has already come a long way, to the point where the U.S. Defense Advanced Research Projects Agency's (DARPA) Tactical Technology Office and the U.S. Marine Corps awarded his company a 30-month, $32-million contract last week to deliver a prototype LS3. This would be the first step in fulfilling the military's call for an autonomous, legged robot that can carry up to 181 kilograms of supplies for at least 32 kilometers without refueling.

A little more than a week after long-simmering programmable logic startup Tabula Inc. emerged from stealth mode, Tier Logic Inc. stepped into the light Wednesday (March 10), offering the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die. Like Tabula, Tier Logic's technology depends on a three-dimensional structure. But while Tabula uses rapid reconfiguration to, in the words of that firm's executives, treat time as the third dimension, Tier Logic's approach separates user circuits and configuration circuits into 3-D stacked layers, creating what the company calls the world's first monolithic 3-D FPGA.

Breadboarding a new circuit is a key skill and an important step in many projects—especially early on, when you need to move wires around and substitute components. But that very flexibility also makes it easy to knock wires out. Eventually, if your project is a keeper, you’re going to want something with a bit more permanence. Printed circuit boards (PCBs) solve all those shortcomings. But most people don’t even consider translating a one-off project into a PCB design. For one thing, PCB fabrication has traditionally been expensive, viable only in commercial quantities. (One alternative is to do it yourself with etches and silk screens, a messy and time-consuming process.) Also, there are technical constraints involved with PCB designs that are daunting to the casual hobbyist. But it turns out that nowadays you can produce a professional PCB very inexpensively.

Analog Devices, Inc., has introduced a pair of Class-D audio amplifiers for smart phones, GPS units and other handheld electronics where premium sound quality offers a major competitive advantage. The SSM2375 and SSM2380 amplifiers provide audio system designers with the option of fixed or programmable gain settings combined with low noise and superior audio performance. The SSM2380 low-power, stereo Class-D amplifier is the first in its class to incorporate an I²C interface, which allows gain stages to be set from 1 dB to 24 dB (plus mute) in 47 distinct steps with no other external components required. The programmable interface also enables independent L/R channel shutdown, a variable low-EMI (electro-magnetic interference) emission control mode, and programmable ALC (automatic level control) functions for speaker protection. The SSM2380 achieves a 100-dB SNR (signal-to-noise ratio) and extends battery life by achieving 93 percent power efficiency at 5 V while running at 1.4 W into an 8-ohm speaker.

Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains. While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures. But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps. In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.