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Events such as natural disasters, military actions, and public safety threats have led to an increased need for robust robots — especially ones that can travel across complex terrain in any dimension. The ability to scale vertical building surfaces or other structures offers unique capabilities in military applications such as urban reconnaissance, sensor deployment, and setting up urban network nodes. SRI's novel clamping technology, called compliant electroadhesion, has enabled the first application of this technology to wall-climbing robots that can help with these situations.  As the name implies, electroadhesion is an electrically controllable adhesion technology. It involves inducing electrostatic charges on a wall substrate using a power supply connected to compliant pads situated on the moving robot. SRI has demonstrated robust clamping to common building materials including glass, wood, metal, concrete, etc. with clamping pressures in the range of 0.5 to 1.5 N per square cm of clamp (0.8 to 2.3 pounds per square inch). The technology works on conductive and non-conductive substrates, smooth or rough materials, and through dust and debris. Unlike conventional adhesives or dry adhesives, the electroadhesion can be modulated or turned off for mobility or cleaning. The technology uses a very small amount of power (on the order of 20 microwatts/Newton weight held) and shows the ability to repeatably clamp to wall substrates that are heavily covered in dust or other debris.

I remember when, a decade ago, Kevin Warwick, a professor at the University of Reading, in the U.K., implanted a radio chip in his own arm. The feat caused quite a stir. The implant allowed him to operate doors, lights, and computers without touching anything. On a second version of the project he could even control an electric wheelchair and produce artificial sensations in his brain using the implanted chip. Warwick had become, in his own words, a cyborg. The idea of a cyborg -- a human-machine hybrid -- is common in science fiction and although the term dates back to the 1960s it still generates a lot of curiosity. I often hear people asking, When will we become cyborgs? When will humans and machines merge? Although some researchers might have specific time frames in mind, I think a better answer is: It's already happening. When we look back at the history of technology, we tend to see distinct periods -- before the PC and after the PC, before the Internet and after the Internet, and so forth -- but in reality most technological advances unfold slowly and gradually. That's particularly true with the technologies that are allowing us to modify and enhance our bodies.

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

Rube Goldberg couldn’t have designed a more elegant confluence of convoluted causal relationships.  Start analyzing the perplexing paradox of the FPGA synthesis market and each link of the chain reveals a bizarre force vector that eventually doubles back onto itself into an unlikely equilibrium that miraculously has held stable for a full decade despite disruptive forces of epic proportions. For over a decade now, Synplify has navigated these waters and has continued to survive and thrive through the unlikeliest of conditions.  Now in the hands of EDA giant Synopsys, the Synplify family of FPGA synthesis tools continues to evolve - with a major upgrade this fall.  When you put a digital design into an FPGA, there are two technologies that determine whether your design fits or doesn’t fit, whether it meets your timing constraints or does not, whether the power consumption will be within your limits (or those of the FPGA), or whether it fails completely, leaving your project at the mercy of major mulligans.   Those two technologies are synthesis and place-and-route. 

Researchers at CMU and Intel are attempting to map and understand human brain activity well enough that individual words can be detected. Currently, giant MRI machines are being used but the future holds smaller devices that can be worn like a helmet according to Dean Pomerleau, senior researcher at Intel. The efficiency and productivity of word detection will be superior to existing technology that allows an operator to simply control a cursor. This technology will no doubt make its way into robotic telepresence applications including remote surgery and construction in dangerous environments such as the ocean and space.

Harmonic balance (hB) analysis is a method used to calculate the nonlinear, steady-state frequency response of electrical circuits. It is extremely well-suited for designs in which transient simulation methods prove acceptable, such as dispersive transmission lines in which circuit time constants are large compared to the period of the simulation frequency, as well as for circuits that have a large number of reactive components. In particular, harmonic balance analysis works extremely well for microwave circuits that are excited with sinusoidal signals, such as mixers and power amplifiers...

INTEL HELD AN EVENT in London last night to talk up its Core i3, i5 and i7 processors. To highlight the ceaseless march of technology and Chipzilla's own adherence to its beloved Moore's Law, the company was showcasing technology from the last 20 years as well as having a few demos about things we may expect to see in the future. Among these was this demonstration about the sorts of applications, such as advanced 3D rendering, that become feasible when a single processor can have 48 or more cores. µ

This book is intended for those who work in or provide components for industries that use digital signal processing (DSP). There is a wide variety of industries that utilize this technology. While the engineers who implement applications using DSP must be very familiar with the technology, there are many others who can benefit from a basic knowledge of its' fundamental principals, which is the goal of this book—to provide a basic tutorial on DSP.

Scientists have great expectations that nanotechnologies will bring them closer to the goal of creating computer systems that can simulate and emulate the brain's abilities for sensation, perception, action, interaction and cognition while rivaling its low power consumption and compact size. DARPA for instance, the U.S. military's research outfit known for projects that are pushing the envelope on what is technologically possible, has a program called SyNAPSE that is trying to develop electronic neuromorphic machine technology that scales to biological levels. Started in late 2008 and funded with $4.9 million, the goal of the initial phase of the SyNAPSE project is to "develop nanometer scale electronic synaptic components capable of adapting the connection strength between two neurons in a manner analogous to that seen in biological systems, as well as, simulate the utility of these synaptic components in core microcircuits that support the overall system architecture."

A little more than a week after long-simmering programmable logic startup Tabula Inc. emerged from stealth mode, Tier Logic Inc. stepped into the light Wednesday (March 10), offering the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die. Like Tabula, Tier Logic's technology depends on a three-dimensional structure. But while Tabula uses rapid reconfiguration to, in the words of that firm's executives, treat time as the third dimension, Tier Logic's approach separates user circuits and configuration circuits into 3-D stacked layers, creating what the company calls the world's first monolithic 3-D FPGA.

Samplify Systems Inc. (Santa Clara, Calif.) has announced an autofocus beamforming technology for ultrasound imaging. The technology uses a 32-channel ultrasound analog front-end receiver module in an ultra-small small-outline dual-in-line configuration based on the SAM1600 family of compressing ADCs.

It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements.  Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.

In high-end audio equipment, careful selection of resistors is one of the best ways to avoid or minimize noise and distortion in the signal path. This paper describes the noise generation in resistors manufactured using the various available resistor technologies and quantifies the noise insertion typical for each type.

bowl and pairing off to come up with a way to create and commercialise sensors and switches that generate their own power. The idea is that the parts will make external power sources redundant - because they can convert energy from body heat, light and vibrations straight into electricity. Self powered electronics have already sporadically been used in technology like wall-mount remote control units for air conditioners, says Nikkei, but existing parts are bulky and cost a couple thousand yen a piece. 3,000 yen is about $35 - which means they're not the best bet, financially, yet.

Single-walled carbon nanotube (SWCNT)-based thin film transistors (TFTs) could be at the core of next-generation flexible electronics – displays, electronic circuits, sensors, memory chips, and other applications that are transitioning from rigid substrates, such as silicon and glass, to flexible substrates. What's holding back commercial applications is that industrial-type manufacturing of large scale SWCNT-based nanoelectronic devices isn't practical yet because controlling the morphology of single-walled carbon nanotubes is still causing headaches for materials engineers.

Opus is Octasic's high-performing, ultra low-power, asynchronous DSP technology optimized for basestations, video processing and media gateway solutions. Asynchronous designs deliver similar computing performance to synchronous designs, but use less silicon and less power. No clock tree No state-elements Less sensitive to process and temperature variations

The goal of Long Term Evolution (LTE) is to achieve higher data rates through more efficient transmission, and thus improving the cellular phone user experience by enabling powerful new devices. The changes required in this technology present new challenges for base station vendors and their suppliers. Supporting 4G systems efficiently requires a number of innovations in DSP design; these innovations are moving the industry toward SoC architectures to support such systems. This paper will explore how TI's new architecture enables the key features in 4G systems.