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Yet another new idea for FPGAs: relays? - Practical Chip Design - Blog on EDN - 1690000169 - 0 views

  • March has seen two significant announcements from FPGA start-ups with innovative architectures: Tabula, with their time-domain-multiplexed architecture, and TierLogic, implementing their routing switches in a layer of thin-film transistors. Both approaches promise to significantly reduce the die size and cost of high-end FPGAs. But before these announcements broke, a relatively unnoticed paper at February's International Symposium on FPGAs described what may be the most radical technology of them all: FPGAs using electromechanical relays. No, this is not an early April Fool's joke, nor is it one of those "let's see if anyone will publish this one" academic exercises. The paper presented work by professors and students at the Stanford University departments of electrical engineering and computer science, and researchers at Altera Corp. The work was supported in part by DARPA funding.
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Embedded.com - Timing Closure on FPGAs - 0 views

  • Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains. While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures. But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps. In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.
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Leveraging FPGA and CPLD digital logic to implement analog to digital converters - 0 views

  • Ted Marena of Lattice Semiconductor Corp., points out that designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function components on their printed circuit board. In addition to these digital functions, FPGAs and CPLDs can also implement common analog functions using an LVDS input, a simple resistor capacitor (RC) circuit and some FPGA or CPLD digital logic elements to create an analog to digital converter (ADC).
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FPGA compilation on-site or in the cloud - 0 views

  • It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements.  Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.
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Delta-Sigma converters for audio output in an infotainment FPGA - 1 views

  • Field programmable gate arrays (FPGAs) present an efficient and inexpensive alternative when it comes to implementing complete embedded systems along with important peripheral functions. The reconfigurable logic circuitry of an FPGA offers tremendous flexibility. A lesser known feature is that the outputs of a digital FPGA also permit various analogue applications.
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| Programmable Logic DesignLine - 0 views

  • Menta SAS and LIRMM have taped out what they believe is the of worlds first MRAM-based FPGA which has patent-protected circuitry enabling compact integration of MRAM and embedded-FPGA solutions. Researchers at the Montpellier Laboratory of Informatics, Robotics and Microelectronics (LIRMM), in France, claimed in October that they had developed a FPGA circuit based on non volatile resistive memory cell.
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How to achieve 1 trillion floating-point operations-per-second in an FPGA - 1 views

  • Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.
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How to achieve timing closure in large, complex FPGA designs - 0 views

  • This article features an example chapter from a new *Hot-off-the-Press* book on FPGA Design that just recently hit the streets in August 2010. This chapter is reproduced here with the kind permission of the publisher – Springer. This book -- FPGA Design: Best Practices for Team-Based Design -- describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed.
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Implementing custom DDR and DDR2 SDRAM external memory interfaces | Programmable Logic ... - 0 views

  • The FPGAs referenced in these articles have complex dedicated I/O circuitries that are primarily designed to support external memory interfaces. The ALTMEMPHY megafunction is designed to support the most common memory standards, such as the DDR and DDR 2 SDRAM and QDR II+/QDR II SRAM (in a burst length of 4) interfaces. The ALTMEMPHY megafunction should be used whenever possible as it is beneficial to use the IP and timing closure methodologies used with these FPGAs, which enables users not to have to create this function manually as compared with using the ALTDLL and ALTDQ_DQS solution. However, the ALTMEMPHY megafunction does not support other external memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2) or customized DDR and DDR 2 SDRAM external memory standards. For these scenarios, use the ALTDLL and ALTDQ_DQS megafunctions to access the FPGA architecture and build a custom external memory interface.
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Implementing custom DDR and DDR2 SDRAM external memory interfaces | Programmable Logic ... - 0 views

  • FPGAs referenced in this article have complex dedicated I/O circuitries that are primarily designed to support EMIF. The ALTMEMPHY megafunction is designed to support the most common memory standards, such as the DDR , DDR2 SDRAM, and QDR II+/QDR II SRAM (in a burst length of 4) interfaces. Other external memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2), or customized DDR and DDR 2 SDRAM external memory standards are not supported. Instead, the ALTDLL and ALTDQ_DQS megafunctions are used to access the FPGA architecture and build a custom EMIF.
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Xilinx, Avnet wrap X-fest seminar series | Programmable Logic DesignLine - 0 views

  • Avnet Electronics Marketing and Xilinx Inc. said they have concluded their five-month, 37-city global X-fest technical seminar series. According to the companies, the free one-day training sessions offered practical, how-to system level design instruction featuring the Spartan-6 and Virtex-6 FPGA families from Xilinx, as well as key enabling technologies from suppliers including Cypress Semiconductor, Intel, Maxim Integrated Products, National Semiconductor, NXP, Texas Instruments and Tyco Electronics. Replays of the events are available online.
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A fork in the road to 28-nm FPGAs | Programmable Logic DesignLine - 0 views

  • How's this for a wedge issue on a slow news week? When Xilinx announced earlier this year that it was changing one of its foundry suppliers from UMC to TSMC for the 28-nm node, it seemed like a blow to differentiation—at least from a process technology standpoint—between Xilinx and Altera, which has been using TSMC for years. But while Xilinx chose to go with TSMC's high-performance/low power process, Altera said this week it is going with TSMC's high-performance process. Altera maintains that customers in the high end communications equipment market are much more concerned about performance than power. Luanne Schirrmeister, senior director of product marketing at Altera, put it this way: "In communications infrastructure, nothing is battery powered. Everything is plugged into a wall."
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ESC - Xilinx Extensible Processing Platform combines best of serial and parallel proces... - 0 views

  • Xilinx Inc. today introduced the architecture for a new Extensible Processing Platform they claim will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenges they face in designing today's embedded systems, which must meet ever-growing demands to perform highly complex functions. The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing - or any combination thereof - needed to meet their application-specific requirements, including lower cost and power.
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Using an FPGA to tame the power beast in consumer handheld MPUs | Power Management Desi... - 0 views

  • Using a programmable device to expand the capabilities of an embedded system, designers can reduce power consumption at the same time By Rahul V. Shah and Vishesh Agrawal
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    Pretty cool and very useful tips.....
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Using an FPGA to tame the power beast in consumer handheld MPUs | Audio DesignLine - 0 views

  • The consumer handheld market is growing by leaps and bounds. With more processing power and increased support for more applications, portable products are cross-pollinating with traditional computing systems even as the product life cycle has decreased considerably in this market segment. As a result, especially in this era of economic slowdown, it is imperative that new products meet the time-to-market window to gain maximum acceptance. A decrease in product life cycles requires a reduced development cycle and an increased emphasis on reusability and reprogrammability. The emerging handheld market is also seeing interesting trends in which each individual device in a family has lower volumes but there is more customization across the series of devices, effectively upping the total unit volumes. The key challenge then becomes how to develop a system that is widely reusable and also customizable. These requirements have led designers increasingly to turn to the FPGA for handheld-product development. The FPGA has become more powerful and feature-rich, while gate counts, area and frequency have increased. FPGA development and turnaround cycles are considerably shorter than those of custom ASICs, and the added advantage of reprogrammability can make the FPGA a more compelling solution for handheld embedded systems.
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Leveraging FPGA in PCB system designs | Industrial Control Designline - 0 views

  • FPGA devices create compelling business drivers generating a tidal wave of FPGA adoption for the implementation of system PCB designs. Obviously, the time to market advantages and capacity/performance characteristics of FPGA devices have delivered on the promise for a viable alternative to more capital resource intensive custom IC/ASIC solutions as well as a successful consolidation vehicle for standard "off the shelf" components in system design creation.
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Module aids Camera Link FPGA image processing | Industrial Control Designline - 1 views

  • National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing. The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.
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electronics technology engineering FPGAs programmable logic devices Microelectronics DSP programming

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Embedded.com - Protecting FPGAs from power analysis security vulnerabilities - 0 views

  • Recent advances in the size and performance of FPGAs, coupled with advantages in time-to-market, field-reconfigurability and lower up-front costs, make FPGAs ideally suited to a wide range of commercial and defense applications [6]. In addition, FPGAs generality and reconfigurability provide important protections against the introduction of Trojan horses during semiconductor manufacturing process[8]. As a result, FPGA applications increasingly involve highly-sensitive intellectual property and trade-secrets, as well as cryptographic keys and algorithms [7].
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