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Using a programmable device to expand the capabilities of an embedded system, designers can reduce power consumption at the same time By Rahul V. Shah and Vishesh Agrawal

Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them. "There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec. On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.

D-Wave Systems, which in 2009 partnered with Google to test a prototype quantum computer for detecting vehicles in images, announced that it has now sold the first commercial quantum computer. The D-Wave quantum computer, called Rainier, solves discrete optimization problems using quantum annealing. The computer was sold to Lockheed-Martin for an undisclosed price. It is supercooled, requires 15 kilowatts, and supports APIs in multiple programming environments including Python, Java, C++, SQL, and MATLAB.