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High Level Synthesis Architectural Optimization Basics In part 1 of this article we introduced basic filter bank theory and used the Synplify DSP High Level Synthesis (HLS) tool to implement an example filter bank into three alternative architectures. In part 2 we dive deeper into these three architectures to better understand how these filters work. We will also examine the HLS optimizations we applied and the resulting benefits. Example Filter Bank Review Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample rate (red) has been chosen and the output sample rate is downsampled by 16 (green).

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before.

Opus is Octasic's high-performing, ultra low-power, asynchronous DSP technology optimized for basestations, video processing and media gateway solutions. Asynchronous designs deliver similar computing performance to synchronous designs, but use less silicon and less power. No clock tree No state-elements Less sensitive to process and temperature variations

The ARM Cortex™-M4 processor is the latest embedded processor by ARM specifically developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors is designed to satisfy the emerging category of flexible solutions specifically targeting the motor control, automotive, power management, embedded audio and industrial automation markets. The Cortex-M4 processor features extended single-cycle multiply-accumulate (MAC) instructions, optimized SIMD arithmetic, saturating arithmetic instructions and an optional single precision Floating Point Unit (FPU). These features build upon the innovative technology that characterizes the ARM Cortex-M series processors…

Multisim 11 is the latest version of its circuit simulation software, with specialized editions for both hands-on learning and professional circuit design. The easy-to-use Multisim software delivers a graphical approach that abstracts the complexities of traditional circuit simulation, helping educators, students and engineers employ advanced circuit analysis technology. The academic edition of Multisim 11 incorporates specialized teaching features and is complemented by circuits textbooks and courseware. This integrated system helps educators engage students and reinforce circuit theory with an interactive, hands-on approach to investigating circuit behavior. Multisim 11 Professional helps engineers optimize circuit designs, minimize errors and reduce prototype iterations. When combined with the new NI Ultiboard 11 layout and routing software, Multisim provides engineers a cost-effective, end-to-end prototyping platform. Its integration with NI LabVIEW measurement software also helps engineers define custom analyses to improve design validation…

Supporting the Wind River Systems VxWorks operating system on Intel architecture is valuable for customers who would like to preserve their application software and evaluate other architectures for comparison purposes or for architecture conversion. Products from Wind River Systems, particularly VxWorks, offer a great opportunity to address multiple architectures with the same real-time operating system (RTOS). Furthermore, the continuous development and migration of multicore platforms has increased the focus on migrating software to multicore and performance optimizations given a specified software workload and certain hardware resources.

Related to the strong demands for virtualization technology, network I/O virtualization has recently become a hot topic and is one of the key topics being discussed at the upcoming Multicore Expo @ ESC. In fact, analyst firm IDC, in a recent white paper titled "Optimizing I/O Virtualization: Preparing the Data Center for Next-Generation Applications", stated that "If I/O is not sufficient, then it could limit all the gains brought about by the virtualization process."

Power and energy are key design considerations across a spectrum of computing solutions, from supercomputers and data centers to handheld phones and other mobile computers. A large body of work focuses on managing power and improving energy efficiency. While prior work is easily summarized in two words—"Avoid waste!"—the challenge is figuring out where and why waste happens and determining how to avoid it. In this article, I discuss how, at a general level, many inefficiencies, or waste, stem from the inherent way system architects address the complex trade-offs in the system-design process. I discuss common design practices that lead to power inefficiencies in typical systems and provide an intuitive categorization of high-level approaches to addressing them. The goal is to provide practitioners—whether in systems, packaging, algorithms, user interfaces, or databases—a set of tools, or "recipes," to systematically reason about and optimize power in their respective domains.

D-Wave Systems, which in 2009 partnered with Google to test a prototype quantum computer for detecting vehicles in images, announced that it has now sold the first commercial quantum computer. The D-Wave quantum computer, called Rainier, solves discrete optimization problems using quantum annealing. The computer was sold to Lockheed-Martin for an undisclosed price. It is supercooled, requires 15 kilowatts, and supports APIs in multiple programming environments including Python, Java, C++, SQL, and MATLAB.