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One of the biggest commercial applications of spintronics in computing to date has been the use of giant magnetoresistance (GMR), the material phenomenon that makes possible the huge storage capacity of today’s hard disk drives. In the awarding of the 2007 Nobel Prize in Physics, GMR was cited as the first big commercial application for nanotechnology. But extending the commercial application of spintronic-enabled systems beyond read heads for HDDs has proven to be a difficult task. One need only look at the seemingly endless travails of NVE Corporation, which in its financial results still shows it greatest revenue growth in contract research as opposed to product sales. While recent research from a team of researchers at Ohio State University and the University of Hamburg in Germany may not turn around the fortunes of spintronics in the short term, it does provide a way to better characterize the spin of electrons and thereby promises better ways of exploiting it for electronics applications. The researchers are reporting in Nature Nanotechnology that they have for the first time been able to create images of the spin direction of electrons.

Ozmo Devices, the leading provider of low-power Wi-Fi Personal Area Network (Wi-Fi PAN) solutions, announced today that it started sampling its OZMO2000 chip to select peripheral manufacturers.  This is the first Wi-Fi solution to overcome the battery life, cost and compatibility issues that have limited the broad adoption of Wi-Fi for HID (human interface device) applications.  The OZMO2000 is currently available for use in Wi-Fi mouse, keyboard and remote control designs.  Furthermore, the solution is compatible with all Wi-Fi-enabled notebooks and desktops that are compatible with Windows 7.

The first textbook of its kind, Programming Massively Parallel Processors: A Hands-on Approach launches today, authored by Dr. David B. Kirk, NVIDIA Fellow and former chief scientist, and Dr. Wen-mei Hwu, who serves at the University of Illinois at Urbana-Champaign as Chair of Electrical and Computer Engineering in the Coordinated Science Laboratory, co-director of the Universal Parallel Computing Research Center and principal investigator of the CUDA Center of Excellence. The textbook, which is 256 pages, is the first aimed at teaching advanced students and professionals the basic concepts of parallel programming and GPU architectures. Published by Morgan Kaufmann, it explores various techniques for constructing parallel programs and reviews numerous case studies. With conventional CPU-based computing no longer scaling in performance and the world’s computational challenges increasing in complexity, the need for massively parallel processing has never been greater. GPUs have hundreds of cores capable of delivering transformative performance increases across a wide range of computational challenges. The rise of these multi-core architectures has raised the need to teach advanced programmers a new and essential skill: how to program massively parallel processors.

D-Wave Systems, which in 2009 partnered with Google to test a prototype quantum computer for detecting vehicles in images, announced that it has now sold the first commercial quantum computer. The D-Wave quantum computer, called Rainier, solves discrete optimization problems using quantum annealing. The computer was sold to Lockheed-Martin for an undisclosed price. It is supercooled, requires 15 kilowatts, and supports APIs in multiple programming environments including Python, Java, C++, SQL, and MATLAB.

A little more than a week after long-simmering programmable logic startup Tabula Inc. emerged from stealth mode, Tier Logic Inc. stepped into the light Wednesday (March 10), offering the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die. Like Tabula, Tier Logic's technology depends on a three-dimensional structure. But while Tabula uses rapid reconfiguration to, in the words of that firm's executives, treat time as the third dimension, Tier Logic's approach separates user circuits and configuration circuits into 3-D stacked layers, creating what the company calls the world's first monolithic 3-D FPGA.

Predicting trends is difficult even by the most connected industry experts, but one trend that's easy to spot is the widespread acceptance of multicore SoC. This is happening for a number of reasons. First, it's been years since the workstation first adopted the multicore processor architecture to solve such issues as increasing performance and power concerns. While the adoption rate in workstations is now saturated and is fully supported by General Purpose OSs (GPOS), the embedded world is just now looking at ways to adopt multicore architecture. Second, several SoC vendors have been providing multicore solutions including Cavium, Freescale, MIPS, and ARM; but up until now, these solutions have been limited to networking and used for performance enhancements rather than for low power. The rest of the embedded industry has had limited hardware options available as low-power design is a driving factor. While the ARM 11 MPCore was ahead of its time, the Cortex-A9 MPCore design is ready for primetime and is gaining acceptance in the embedded marketplace. As a result, SoC vendors have adopted the Cortex-A9 MPCore hardware as a basis for their next generation designs. Over a year ago, Texas Instruments pre-announced their next-generation OMAP designs in the OMAP 4 with a dual-core Cortex-A9 MPCore, scheduled for production in the second-half of 2010. ST Microsystems has pre-announced their next generation consumer devices which will be based on the Cortex A9 MPCore.

Menta SAS and LIRMM have taped out what they believe is the of worlds first MRAM-based FPGA which has patent-protected circuitry enabling compact integration of MRAM and embedded-FPGA solutions. Researchers at the Montpellier Laboratory of Informatics, Robotics and Microelectronics (LIRMM), in France, claimed in October that they had developed a FPGA circuit based on non volatile resistive memory cell.

In earlier articles on intelligent sensor design, we saw how valuable they can be to both end users and those who manufacture and sell them. It’s now time to delve more deeply into what it takes to make intelligent sensors work.   The first step in that journey is to develop a solid, intuitive understanding of the principles of digital signal processing(DSP). Unlike many introductory DSP articles and texts, the focus here will be on presenting and using the important concepts rather than deriving them, for the simple reason that addressing the subject in depth is a book-sized, not a chapter-sized, project.

Imagine that a guest is about to depart from your house. She (or he) pauses to check her appearance in an antique-looking mirror mounted near the front door. Suddenly, the image of your guest undergoes a Matrix-like 'ripple' and is replaced with a strange face saying… …actually, we'll move on to consider what the face might say in a moment, but first let me introduce you to a few underlying concepts. Just a few days ago as I pen these words, I came across about a very cool website that describes a really cunning idea called a Magic Mirror (http://diymagicmirror.com).

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

A research project will be conducted this week in Linz, Austria, to discover what the ideal interaction between people and humanoid robots ought to be in the future, Honda R&D and Ars Electronica Futurelab announced today. The research, the first of its kind in Europe, will involve members of the public directly interacting with ASIMO, Honda's humanoid robot.

Events such as natural disasters, military actions, and public safety threats have led to an increased need for robust robots — especially ones that can travel across complex terrain in any dimension. The ability to scale vertical building surfaces or other structures offers unique capabilities in military applications such as urban reconnaissance, sensor deployment, and setting up urban network nodes. SRI's novel clamping technology, called compliant electroadhesion, has enabled the first application of this technology to wall-climbing robots that can help with these situations.  As the name implies, electroadhesion is an electrically controllable adhesion technology. It involves inducing electrostatic charges on a wall substrate using a power supply connected to compliant pads situated on the moving robot. SRI has demonstrated robust clamping to common building materials including glass, wood, metal, concrete, etc. with clamping pressures in the range of 0.5 to 1.5 N per square cm of clamp (0.8 to 2.3 pounds per square inch). The technology works on conductive and non-conductive substrates, smooth or rough materials, and through dust and debris. Unlike conventional adhesives or dry adhesives, the electroadhesion can be modulated or turned off for mobility or cleaning. The technology uses a very small amount of power (on the order of 20 microwatts/Newton weight held) and shows the ability to repeatably clamp to wall substrates that are heavily covered in dust or other debris.

RoweBots Research, Inc., a supplier of tiny embedded POSIX RTOS products, today announced the launch and release of UnisonTM Version 5 and the open-source version of Unison Version 4. These two ultra-tiny embedded-Linux and POSIX compatible RTOSs open Renesas Technology Corp.’s SH-2A Microcontroller (MCU) family to Linux and POSIX compatible development for the first time.

Within the next three years, the U.S. military will test the feasibility of sending a quadruped robot out into the field as a trusty pack mule to carry supplies for its troops, wherever they go. If the testing goes well for Boston Dynamics's Legged Squad Support System (LS3), company founder Marc Raibert will have come a long way from the one-legged hopping robots he pioneered in the 1980s. Actually Raibert has already come a long way, to the point where the U.S. Defense Advanced Research Projects Agency's (DARPA) Tactical Technology Office and the U.S. Marine Corps awarded his company a 30-month, $32-million contract last week to deliver a prototype LS3. This would be the first step in fulfilling the military's call for an autonomous, legged robot that can carry up to 181 kilograms of supplies for at least 32 kilometers without refueling.

Ever since graphene was first produced in a lab at the University of Manchester in 2004, researchers around the world have been fascinated with its potential in electronics applications. Graphene possessed all the benefits of carbon nanotubes (CNTs), namely its charged-carrier mobility, but it didn’t have any of the down sides, such as CNTs’ need for different processing techniques than silicon and the intrinsic difficulty of creating interconnects for CNTs. But all was not easy for applying graphene to electronics applications. One of the fundamental problems for graphene was its lack of a band gap, which left it with a very low on-off ratio measured at about 10 as compared to in the 100s for silicon. Now this fundamental hurdle has been overcome. Based on research led by Phaedon Avouris at IBM’s IBM T.J. Watson Research Center, Yorktown Heights, New York, IBM is reporting that they have created a significant band gap in graphene.

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.