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TTE Systems' RapidiTTy IDE provides a self-contained environment for developers who wish to create "time-triggered" microcontroller software in order to improve overall system reliability. RapidiTTy (Figure 1, below) is intended to address deeply-embedded applications including control and monitoring operations in medical, defence, automotive and industrial sectors, as well as in white and brown goods.

The embedded world is constantly changing. You might not have noticed, but if you take a minute to recall what a microcontroller system was like 10 years ago and compare it to today's latest microcontroller systems, you will find that PCB design, component packages, level of integration, clock speed, and memory size have all going through several generations of change. One of the hottest topics in this area is when will the last of remaining 8-bit microcontroller users start to move away from legacy architectures and move to modern 32-bit processor architectures like the ARM Cortex-M based microcontroller family. Over the last few years there has been a strong momentum of embedded developers starting the migration to 32-bit microcontrollers and, in this multi-part article, we will take a look at some of the factors accelerating this migration.

Within the next three years, the U.S. military will test the feasibility of sending a quadruped robot out into the field as a trusty pack mule to carry supplies for its troops, wherever they go. If the testing goes well for Boston Dynamics's Legged Squad Support System (LS3), company founder Marc Raibert will have come a long way from the one-legged hopping robots he pioneered in the 1980s. Actually Raibert has already come a long way, to the point where the U.S. Defense Advanced Research Projects Agency's (DARPA) Tactical Technology Office and the U.S. Marine Corps awarded his company a 30-month, $32-million contract last week to deliver a prototype LS3. This would be the first step in fulfilling the military's call for an autonomous, legged robot that can carry up to 181 kilograms of supplies for at least 32 kilometers without refueling.

The potential for the QTC material to transition from an insulator to a conductor (i.e. change its electrical property) is influenced by how much deformation the material is experiencing as a result of the applied mechanical pressure. QTC can be used to produce low profile, low cost, pressure activated switches or sensors that display variable resistance with applied force and return to a quiescent state when the force is removed. The difference between a QTC switch and a QTC sensor is arguably only the speed and amount of physical input required to achieve the required switching point or resistance range.

PC-compatible industrial computers are increasing in computing power at a rapid rate due to the availability of multi-core microprocessor chips, and Microsoft Windows has become the de-facto software platform for implementing human-machine interfaces (HMIs). PCs are also becoming more reliable. With these trends, the practice of building robotic systems as complex multi-architecture, multi-platform systems is being challenged. It is now becoming possible to integrate all the functions of machine control and HMI into a single platform, without sacrificing performance and reliability of processing. Through new developments in software, we are seeing industrial systems evolving to better integrate Windows with real-time functionality such as machine vision and motion control. Software support to simplify motion control algorithm implementation already exists for the Intel processor architecture.

The first textbook of its kind, Programming Massively Parallel Processors: A Hands-on Approach launches today, authored by Dr. David B. Kirk, NVIDIA Fellow and former chief scientist, and Dr. Wen-mei Hwu, who serves at the University of Illinois at Urbana-Champaign as Chair of Electrical and Computer Engineering in the Coordinated Science Laboratory, co-director of the Universal Parallel Computing Research Center and principal investigator of the CUDA Center of Excellence. The textbook, which is 256 pages, is the first aimed at teaching advanced students and professionals the basic concepts of parallel programming and GPU architectures. Published by Morgan Kaufmann, it explores various techniques for constructing parallel programs and reviews numerous case studies. With conventional CPU-based computing no longer scaling in performance and the world’s computational challenges increasing in complexity, the need for massively parallel processing has never been greater. GPUs have hundreds of cores capable of delivering transformative performance increases across a wide range of computational challenges. The rise of these multi-core architectures has raised the need to teach advanced programmers a new and essential skill: how to program massively parallel processors.

In case you haven’t realized it, the new trend in computer chip technology is multi-core. This is where most of the speed improvements moving forward will come from on our computers. To take full advantage of this however it is necessary to design your applications using Parallel Programming practices, also known as "parallelism". In today’s episode, we will meet with Stephen Toub, who will share with us some of the overarching concepts associated with parallelism, and some of the ways we are trying to empower developers to develop applications to take advantage of it.

You just built a breadboard of your expert design. You did all the simulations needed before going to layout, and reviewed the manufacturer's suggested techniques for a good thermal design for the particular package chosen. You even did your due diligence in going through the initial thermal analysis equations on paper to be sure not to exceed IC junction temperatures with a comfortable margin. But wait, you turn on the power and the IC is pretty hot to the touch. You are uncomfortable with this (not to mention the concern of your thermal experts and reliability people). Now what do you do?

The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these performances.In this article, we will detail how to assess rigorously power consumption, area, speed, code density and processing power for an embedded MCU. For each performance, we will describe how the parameters have to be selected to enable a fair comparison between processor cores.

While the new multicore system on chip (SoC) signal-processing architecture announced by Texas Instruments this week at Mobile World Congress hits all the right notes with respect to what's needed in next-generation basestation designs, it rings a bit hollow given how sketchy the architectural details remain when contrasted with more 'real' announcements from the likes of Freescale. For sure, the requirements of next-generation basestations will push all architectures to their limits and beyond. Balancing lower power and lower cost with increasingly parallel, math-intensive processing to meet multiuser demands for high-data-rate data in 3GPP Long Term Evolution (LTE) Release 8 all-IP networks is not going to be easy, especially with the introduction of MIMO, beam forming, OFDMA and many other enhancements engineered to maximize spectral efficiency.

Just as photographic film was mostly replaced by silicon image chips, now quantum film threats to replace the conventional CMOS image sensors in digital cameras. Made from materials similar to conventional film—a polymer with embedded particles—instead of silver grains like photographic film the embedded particles are quantum dots. Quantum films can image scenes with more pixel resolution, according to their inventors, InVisage Inc., offering four-times better sensitivity for ultra-high resolution sensors that are cheaper to manufacture.

Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate mark. With designs of this magnitude, the need for fast flows has never been greater. At the same time, designers are seeking rapid feedback on their ASIC or FPGA designs by implementing quick prototypes or initial designs on FPGA-based boards. These prototypes or designs allow designers to start development, verification and debug of the design—in the context of system software and hardware—and also to fine tune algorithms in the design architecture. Quick and intuitive debug iterations to incorporate fixes are of great value. The ability to perform design updates that don't completely uproot all parts of the design that have already been verified is also a bonus! Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.

Breadboarding a new circuit is a key skill and an important step in many projects—especially early on, when you need to move wires around and substitute components. But that very flexibility also makes it easy to knock wires out. Eventually, if your project is a keeper, you’re going to want something with a bit more permanence. Printed circuit boards (PCBs) solve all those shortcomings. But most people don’t even consider translating a one-off project into a PCB design. For one thing, PCB fabrication has traditionally been expensive, viable only in commercial quantities. (One alternative is to do it yourself with etches and silk screens, a messy and time-consuming process.) Also, there are technical constraints involved with PCB designs that are daunting to the casual hobbyist. But it turns out that nowadays you can produce a professional PCB very inexpensively.

Tiny semiconductor dots could lead to a new type of circuit based on magnetism rather than current flow. At least that’s the hope of researchers who’ve made the dots and are hoping to build them into a workable device. ”We want to make it into a so-called nonvolatile transistor,” says Kang Wang, head of the Device Research Laboratory at the University of California, Los Angeles. Such a ”spintronic” transistor would retain its logic state in the absence of current and require less power to switch a bit, reducing the electrical power required by a computer chip by as much as 99 percent. Wang’s research, supported in part by Intel, was published in March in the online version of Nature Materials. Where electronic transistors rely on the presence or absence of current to register the ones and zeros of digital logic, spintronic transistors depend on ”spin,” a quantum characteristic of the electron. Picture the electron as a rotating globe. When the north pole is pointing upward, that’s spin up; when pointing the other way, it’s spin down. When the spins of most electrons are aligned, the material is magnetic. When their spins are random, the material isn’t. An applied current can align or randomize the spins, allowing for spin-based switches.

One of the biggest commercial applications of spintronics in computing to date has been the use of giant magnetoresistance (GMR), the material phenomenon that makes possible the huge storage capacity of today’s hard disk drives. In the awarding of the 2007 Nobel Prize in Physics, GMR was cited as the first big commercial application for nanotechnology. But extending the commercial application of spintronic-enabled systems beyond read heads for HDDs has proven to be a difficult task. One need only look at the seemingly endless travails of NVE Corporation, which in its financial results still shows it greatest revenue growth in contract research as opposed to product sales. While recent research from a team of researchers at Ohio State University and the University of Hamburg in Germany may not turn around the fortunes of spintronics in the short term, it does provide a way to better characterize the spin of electrons and thereby promises better ways of exploiting it for electronics applications. The researchers are reporting in Nature Nanotechnology that they have for the first time been able to create images of the spin direction of electrons.

Let’s face it. Most of the gear you use at work or play has multicore processors in it. Your laptop has them (the CPU itself has two cores, and the dedicated graphics processor has many more). That game console in the living room has still more, and even a high-end smartphone typically has a CPU and graphics core on a single chip. Out of sight but definitely not out of mind–particularly if they cease working–are the servers and high-throughput network routers, all which have numerous multicore processors in them. The multiple cores in these devices work in concert to provide quick responses to user queries or to manage the smooth flow of data throughout the office.