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The ARM Cortex™-M4 processor is the latest embedded processor by ARM specifically developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors is designed to satisfy the emerging category of flexible solutions specifically targeting the motor control, automotive, power management, embedded audio and industrial automation markets. The Cortex-M4 processor features extended single-cycle multiply-accumulate (MAC) instructions, optimized SIMD arithmetic, saturating arithmetic instructions and an optional single precision Floating Point Unit (FPU). These features build upon the innovative technology that characterizes the ARM Cortex-M series processors…

A Product How-To on building a unified control environment using architectures such as TI’s Stellaris ARM Cortex-M3-based MCUs or Cortex-A8-based Sitara AM35x MPUs.

When Pantelis Georgiou and his fellow biomedical engineers at Imperial College London decided to design an intelligent insulin pump for diabetes patients, they started at the source. "We asked ourselves, what does a pancreas do to control blood glucose?" Georgiou recalls. The answer is pretty well known: The organ relies primarily on two populations of cells—beta cells, to secrete insulin when blood glucose is high, and alpha cells, which release a hormone called glucagon when glucose levels are low. "We simulated them both in microchip form," Georgiou says. This biomimetic approach diverges from today's dominant method of delivering only insulin using a relatively simple control system.

You just built a breadboard of your expert design. You did all the simulations needed before going to layout, and reviewed the manufacturer's suggested techniques for a good thermal design for the particular package chosen. You even did your due diligence in going through the initial thermal analysis equations on paper to be sure not to exceed IC junction temperatures with a comfortable margin. But wait, you turn on the power and the IC is pretty hot to the touch. You are uncomfortable with this (not to mention the concern of your thermal experts and reliability people). Now what do you do?

National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing. The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.

DMA is used in almost every complex system or subsystems, but it's observed that teams either build the DMA controller from scratch for each project for specific application or take the existing DMAC available from elsewhere. This article discusses the architecture of DMAC that can be used with any kind of Bus, configuration (parallel, serial transfers), can be connected to any kind of ports, most importantly any kind of software assumptions can be implemented in the DMAC very easily.

NXP BV (Eindhoven, The Netherlands) has said it will demonstrate a microcontroller based on the ARM Cortex-M4 at the Embedded Systems Conference in San Jose, California. NXP was one of the first companies to license the Cortex-M4 processor core and a chip has been implemented using a low-leakage 90-nm process technology. This enables performance in excess of 150-MHz clock frequency, NXP said. NXP has added proprietary power-down techniques to reduce power consumption. The ESC Silicon Valley demo will show that a 7-channel audio graphic equalizer application processing 32-bit precision audio data requires only 12 MHz of CPU bandwidth using the Cortex-M4 DSP extensions, and 60 MIPs without. The core includes DSP extensions not usually found inside a microcontroller and NXP's implementation are aimed at a broad set of applications including motor control, digital power control and embedded audio.

Understand an accelerator's particle-beam measurement and control challenge, and how engineers met it with leading-edge digitizing systems and associated techniques

Synopsys, Inc., has unveiled the DesignWare Ethernet Quality-of-Service (QoS) Controller IP which implements the new IEEE specifications for audio video bridging (AVB) features. The DesignWare Ethernet IP solution supports the new IEEE 802.1AS and 802.1-Qav version D6.0 specifications. These specifications enable efficient networking of streaming audio video (AV) applications through IEEE 802.1 networks found in consumer electronics, automotive AV and professional sound system products. Synopsys' DesignWare Ethernet QoS Controller, which supports 10/100/1G data transfer speeds, allows designers to develop system-on-chips (SoCs) that deliver time-synchronized, low-latency audio and video over Ethernet networks with exceptional quality-of-service while retaining compatibility with legacy networks.

In traditional short-haul microwave transmission (that is, line-of-sight microwave transmissions operating in the 18 GHz and 23 GHz radio bands),RF design engineers typically are concerned with signal aspects such as fade margins, signal reflections, multipath signals, and so forth. Like an accountant seeking to balance a financial spreadsheet, an RF design engineer normally creates an RF budget table, expressed in decibels (dB), in order to establish a wireless design. Aspects like transmit power and antenna gain are registered in the assets (or plus) column, and free space attenuation, antenna alignment, and atmospheric losses are noted in the liabilities (or minus) column. The goal is to achieve a positive net signal strength adequate to support the wireless path(s) called for in the design.

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.

Researchers at CMU and Intel are attempting to map and understand human brain activity well enough that individual words can be detected. Currently, giant MRI machines are being used but the future holds smaller devices that can be worn like a helmet according to Dean Pomerleau, senior researcher at Intel. The efficiency and productivity of word detection will be superior to existing technology that allows an operator to simply control a cursor. This technology will no doubt make its way into robotic telepresence applications including remote surgery and construction in dangerous environments such as the ocean and space.

Analog Devices, Inc., has introduced a pair of Class-D audio amplifiers for smart phones, GPS units and other handheld electronics where premium sound quality offers a major competitive advantage. The SSM2375 and SSM2380 amplifiers provide audio system designers with the option of fixed or programmable gain settings combined with low noise and superior audio performance. The SSM2380 low-power, stereo Class-D amplifier is the first in its class to incorporate an I²C interface, which allows gain stages to be set from 1 dB to 24 dB (plus mute) in 47 distinct steps with no other external components required. The programmable interface also enables independent L/R channel shutdown, a variable low-EMI (electro-magnetic interference) emission control mode, and programmable ALC (automatic level control) functions for speaker protection. The SSM2380 achieves a 100-dB SNR (signal-to-noise ratio) and extends battery life by achieving 93 percent power efficiency at 5 V while running at 1.4 W into an 8-ohm speaker.

When the Arduino Duemilanove microcontroller appeared in 2005, it featured a set of female pin headers exposing most of the pins of the ATmega168 for easy hacking and for connecting accessory boards known as 'Shields'. The purpose of a shield is to provide new plug-and-play functionality to the host microcontroller, such as circuit prototyping, motion control, sensor integration, network and radio communication, or gaming interfaces, without worrying too much about the hardware implementation details. Seven years after the birth of the original Arduino, new shields keep coming out and are being cataloged on http://shieldlist.org/, a testament to the versatility of the design. It is also simple to build a DIY shield when nothing out there will meet your needs or when you want to understand how the shield concept works from the ground up.

High Level Synthesis Architectural Optimization Basics In part 1 of this article we introduced basic filter bank theory and used the Synplify DSP High Level Synthesis (HLS) tool to implement an example filter bank into three alternative architectures. In part 2 we dive deeper into these three architectures to better understand how these filters work. We will also examine the HLS optimizations we applied and the resulting benefits. Example Filter Bank Review Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample rate (red) has been chosen and the output sample rate is downsampled by 16 (green).

Single-walled carbon nanotube (SWCNT)-based thin film transistors (TFTs) could be at the core of next-generation flexible electronics – displays, electronic circuits, sensors, memory chips, and other applications that are transitioning from rigid substrates, such as silicon and glass, to flexible substrates. What's holding back commercial applications is that industrial-type manufacturing of large scale SWCNT-based nanoelectronic devices isn't practical yet because controlling the morphology of single-walled carbon nanotubes is still causing headaches for materials engineers.

Events such as natural disasters, military actions, and public safety threats have led to an increased need for robust robots — especially ones that can travel across complex terrain in any dimension. The ability to scale vertical building surfaces or other structures offers unique capabilities in military applications such as urban reconnaissance, sensor deployment, and setting up urban network nodes. SRI's novel clamping technology, called compliant electroadhesion, has enabled the first application of this technology to wall-climbing robots that can help with these situations.  As the name implies, electroadhesion is an electrically controllable adhesion technology. It involves inducing electrostatic charges on a wall substrate using a power supply connected to compliant pads situated on the moving robot. SRI has demonstrated robust clamping to common building materials including glass, wood, metal, concrete, etc. with clamping pressures in the range of 0.5 to 1.5 N per square cm of clamp (0.8 to 2.3 pounds per square inch). The technology works on conductive and non-conductive substrates, smooth or rough materials, and through dust and debris. Unlike conventional adhesives or dry adhesives, the electroadhesion can be modulated or turned off for mobility or cleaning. The technology uses a very small amount of power (on the order of 20 microwatts/Newton weight held) and shows the ability to repeatably clamp to wall substrates that are heavily covered in dust or other debris.

With the consumer demand for richer content and its resultant , increasing high data bandwidth continuing to drive communications systems, coding for error control has become extraordinarily important. One way to improve the bit error rate (BER), while maintaining high data reliability, is to use an error correction technique like the Viterbi algorithm. Originally conceived by Andrew Viterbi as an error-correction scheme for noisy digital communication, the Viterbi algorithm provides an efficient method for forward error correction (FEC) that improves channel reliability. Today, it is used in many digital communications systems in applications as diverse as CDMA and GSM digital cellular, dial-up modems, satellite, deep-space communications and 802.11 wireless LANs. It is also commonly used in speech recognition, keyword spotting and computational linguistics.

The MAX13171E along with the MAX13173E/ MAX13175E, form a complete pin-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that support the V.28 (RS-232), V.10/V.11 (RS-449/V.36, RS-530, RS-530A, X.21), and V.35 protocols. The MAX13171E transceivers carry the high-speed clock and data signals, while the MAX13173E transceivers carry the control signals. The MAX13171E can be terminated by the MAX13175E pin-selectable resistor termination network. The MAX13175E contains six pin-selectable, multiprotocol cable termination networks.