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Multisim 11 is the latest version of its circuit simulation software, with specialized editions for both hands-on learning and professional circuit design. The easy-to-use Multisim software delivers a graphical approach that abstracts the complexities of traditional circuit simulation, helping educators, students and engineers employ advanced circuit analysis technology. The academic edition of Multisim 11 incorporates specialized teaching features and is complemented by circuits textbooks and courseware. This integrated system helps educators engage students and reinforce circuit theory with an interactive, hands-on approach to investigating circuit behavior. Multisim 11 Professional helps engineers optimize circuit designs, minimize errors and reduce prototype iterations. When combined with the new NI Ultiboard 11 layout and routing software, Multisim provides engineers a cost-effective, end-to-end prototyping platform. Its integration with NI LabVIEW measurement software also helps engineers define custom analyses to improve design validation…

There are severe flaws within the Harmonic-Balance and SPICE programs now widely used. Mentioned as far back as within an abstract of Session WSO at the 2008 IEEE International Microwave Symposium: "Even though nonlinear circuit-analysis software has been in use for many years, users still have difficulty obtaining valid results with existing methods.  Recognized problems include poor accuracy, convergence difficulties, long simulation times, and unstable results (i.e., results that vary greatly with minor changes in parameters).  These problems are encountered in both harmonic-balance and time-domain simulations."

While the topic of timing has already been raised in previous parts in this series, the discussion here will be expanded to include the execution and response time of the software functions. When discussing timing in embedded software, there are typically two types of timing requirements, rate of execution and response time. Rate of execution deals with the event-to-event timing within a software function. It can be the timing between changes in an output, time between samples of an input, or some combination of both.

TTE Systems' RapidiTTy IDE provides a self-contained environment for developers who wish to create "time-triggered" microcontroller software in order to improve overall system reliability. RapidiTTy (Figure 1, below) is intended to address deeply-embedded applications including control and monitoring operations in medical, defence, automotive and industrial sectors, as well as in white and brown goods.

In many instances, the way embedded software is structured and how it interacts with the hardware in a system can have a profound effect on the transient immunity performance of a system. It can be impractical and costly to completely eliminate transients at the hardware level, so the system and software designers should plan for the occasional erroneous signal or power glitch that could cause the software to perform erratically. Erratic actions on the part of the software can be classified into two different categories:

Supporting the Wind River Systems VxWorks operating system on Intel architecture is valuable for customers who would like to preserve their application software and evaluate other architectures for comparison purposes or for architecture conversion. Products from Wind River Systems, particularly VxWorks, offer a great opportunity to address multiple architectures with the same real-time operating system (RTOS). Furthermore, the continuous development and migration of multicore platforms has increased the focus on migrating software to multicore and performance optimizations given a specified software workload and certain hardware resources.

In a recent video, Willow Garage researcher Eitan Marder-Eppstein describes the open-source navigation stack they've released as version 1.0. The code, available at http://ros.org/wiki/navigation, was designed to be flexible and cross-platform, he says, and could be used in anything from a small iRobot Create-based bot to a large multi-sensor robot like Willow's own PR2 (which Spectrum has covered in detail here and here).

PC-compatible industrial computers are increasing in computing power at a rapid rate due to the availability of multi-core microprocessor chips, and Microsoft Windows has become the de-facto software platform for implementing human-machine interfaces (HMIs). PCs are also becoming more reliable. With these trends, the practice of building robotic systems as complex multi-architecture, multi-platform systems is being challenged. It is now becoming possible to integrate all the functions of machine control and HMI into a single platform, without sacrificing performance and reliability of processing. Through new developments in software, we are seeing industrial systems evolving to better integrate Windows with real-time functionality such as machine vision and motion control. Software support to simplify motion control algorithm implementation already exists for the Intel processor architecture.

Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate mark. With designs of this magnitude, the need for fast flows has never been greater. At the same time, designers are seeking rapid feedback on their ASIC or FPGA designs by implementing quick prototypes or initial designs on FPGA-based boards. These prototypes or designs allow designers to start development, verification and debug of the design—in the context of system software and hardware—and also to fine tune algorithms in the design architecture. Quick and intuitive debug iterations to incorporate fixes are of great value. The ability to perform design updates that don't completely uproot all parts of the design that have already been verified is also a bonus! Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before.

DMA is used in almost every complex system or subsystems, but it's observed that teams either build the DMA controller from scratch for each project for specific application or take the existing DMAC available from elsewhere. This article discusses the architecture of DMAC that can be used with any kind of Bus, configuration (parallel, serial transfers), can be connected to any kind of ports, most importantly any kind of software assumptions can be implemented in the DMAC very easily.

A product can be of low quality for several reasons, such as it was shoddily manufactured, its components were improperly designed, its architecture was poorly conceived, and the product's requirements were poorly understood. Quality must be designed in. You can't test out enough bugs to deliver a high-quality product. The quality assurance (QA) process is vital for the delivery of a satisfactory system. In this last part in this series, we will concentrate on portions of the methodology particularly aimed at improving the quality of the resulting system. The software testing techniques described earlier in this series constitute one component of quality assurance, but the pursuit of quality extends throughout the design flow. For example, settling on the proper requirements and specification cannot be overlooked as an important determinant of quality. If the system is too difficult to design, it will probably be difficult to keep it working properly.

When Pantelis Georgiou and his fellow biomedical engineers at Imperial College London decided to design an intelligent insulin pump for diabetes patients, they started at the source. "We asked ourselves, what does a pancreas do to control blood glucose?" Georgiou recalls. The answer is pretty well known: The organ relies primarily on two populations of cells—beta cells, to secrete insulin when blood glucose is high, and alpha cells, which release a hormone called glucagon when glucose levels are low. "We simulated them both in microchip form," Georgiou says. This biomimetic approach diverges from today's dominant method of delivering only insulin using a relatively simple control system.

The center piece of our toolset is the software integrated development environment or IDE. MPLAB IDE has enjoyed many years of evolution cracking Microchip’s popular catalogue of micro controllers and digital signal controllers. This presentation will cover these topics. Look at MPLAB and its components. An MPLAB IDE overview, MPLAB’s hardware components including starter kits and demonstration and evaluation kits and finally we attempt to answer the question why use Microchip tools.

DSP core licensor Ceva Inc. is due to unveil a software-programmable multimedia video processor architecture at the Mobile World Congress in Barcelona next week. The multicore architecture, called MM3000, which comes complete with C compilers, power management provision and an RTOS/multithreading scheduler is intended to be able to process any and all video codecs up to the highest resolutions and frame rates currently available as well as future codecs for things like 3-D video.

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.