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On Monday, National Instruments announced one such platform. It's called LabView Robotics. In addition to LabView, the popular data-acquisition application, the package includes a bunch of tools specific to robotics. It can import codes in various formats (C, C++, Matlab, VHDL), offers a library of drivers for a wide variety of sensors and actuators, and has modules for implementation of real-time and embedded hardware. NI says engineers could use the package to both design and run their robotic systems. 

You just built a breadboard of your expert design. You did all the simulations needed before going to layout, and reviewed the manufacturer's suggested techniques for a good thermal design for the particular package chosen. You even did your due diligence in going through the initial thermal analysis equations on paper to be sure not to exceed IC junction temperatures with a comfortable margin. But wait, you turn on the power and the IC is pretty hot to the touch. You are uncomfortable with this (not to mention the concern of your thermal experts and reliability people). Now what do you do?

Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them. "There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec. On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.

While the new multicore system on chip (SoC) signal-processing architecture announced by Texas Instruments this week at Mobile World Congress hits all the right notes with respect to what's needed in next-generation basestation designs, it rings a bit hollow given how sketchy the architectural details remain when contrasted with more 'real' announcements from the likes of Freescale. For sure, the requirements of next-generation basestations will push all architectures to their limits and beyond. Balancing lower power and lower cost with increasingly parallel, math-intensive processing to meet multiuser demands for high-data-rate data in 3GPP Long Term Evolution (LTE) Release 8 all-IP networks is not going to be easy, especially with the introduction of MIMO, beam forming, OFDMA and many other enhancements engineered to maximize spectral efficiency.

25 March 2010—Nowadays, a phone that doesn’t know where it is or where it’s going can’t really call itself ”smart.” To orient themselves properly, smartphones require not just GPS capability but also an electronic compass, an accelerometer, and increasingly, digital gyroscopes. The point of a gyroscope is to sense any change in an object’s axis of rotation. Up until now, gyroscopes measured movement around the three axes with three sensors—one for pitch, one for yaw, and another for roll. At most, two of these sensors would be combined on a single die. The best you could do was, say, match up a 3- by 5- by 1-millimeter yaw sensor with a 4- by 5- by 1-mm sensor that would detect pitch and roll. But on 15 February, STMicroelectronics unveiled  a 4- by 4- by 1-mm gyroscope whose single sensing structure tracks all three angular motions. It’s a triumph of microelectromechanical systems (MEMS) engineering.

March has seen two significant announcements from FPGA start-ups with innovative architectures: Tabula, with their time-domain-multiplexed architecture, and TierLogic, implementing their routing switches in a layer of thin-film transistors. Both approaches promise to significantly reduce the die size and cost of high-end FPGAs. But before these announcements broke, a relatively unnoticed paper at February's International Symposium on FPGAs described what may be the most radical technology of them all: FPGAs using electromechanical relays. No, this is not an early April Fool's joke, nor is it one of those "let's see if anyone will publish this one" academic exercises. The paper presented work by professors and students at the Stanford University departments of electrical engineering and computer science, and researchers at Altera Corp. The work was supported in part by DARPA funding.

When the Arduino Duemilanove microcontroller appeared in 2005, it featured a set of female pin headers exposing most of the pins of the ATmega168 for easy hacking and for connecting accessory boards known as 'Shields'. The purpose of a shield is to provide new plug-and-play functionality to the host microcontroller, such as circuit prototyping, motion control, sensor integration, network and radio communication, or gaming interfaces, without worrying too much about the hardware implementation details. Seven years after the birth of the original Arduino, new shields keep coming out and are being cataloged on http://shieldlist.org/, a testament to the versatility of the design. It is also simple to build a DIY shield when nothing out there will meet your needs or when you want to understand how the shield concept works from the ground up.

National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing. The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.

Field programmable gate arrays (FPGAs) present an efficient and inexpensive alternative when it comes to implementing complete embedded systems along with important peripheral functions. The reconfigurable logic circuitry of an FPGA offers tremendous flexibility. A lesser known feature is that the outputs of a digital FPGA also permit various analogue applications.