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Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains. While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures. But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps. In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.

Within the next three years, the U.S. military will test the feasibility of sending a quadruped robot out into the field as a trusty pack mule to carry supplies for its troops, wherever they go. If the testing goes well for Boston Dynamics's Legged Squad Support System (LS3), company founder Marc Raibert will have come a long way from the one-legged hopping robots he pioneered in the 1980s. Actually Raibert has already come a long way, to the point where the U.S. Defense Advanced Research Projects Agency's (DARPA) Tactical Technology Office and the U.S. Marine Corps awarded his company a 30-month, $32-million contract last week to deliver a prototype LS3. This would be the first step in fulfilling the military's call for an autonomous, legged robot that can carry up to 181 kilograms of supplies for at least 32 kilometers without refueling.

A product can be of low quality for several reasons, such as it was shoddily manufactured, its components were improperly designed, its architecture was poorly conceived, and the product's requirements were poorly understood. Quality must be designed in. You can't test out enough bugs to deliver a high-quality product. The quality assurance (QA) process is vital for the delivery of a satisfactory system. In this last part in this series, we will concentrate on portions of the methodology particularly aimed at improving the quality of the resulting system. The software testing techniques described earlier in this series constitute one component of quality assurance, but the pursuit of quality extends throughout the design flow. For example, settling on the proper requirements and specification cannot be overlooked as an important determinant of quality. If the system is too difficult to design, it will probably be difficult to keep it working properly.

D-Wave Systems, which in 2009 partnered with Google to test a prototype quantum computer for detecting vehicles in images, announced that it has now sold the first commercial quantum computer. The D-Wave quantum computer, called Rainier, solves discrete optimization problems using quantum annealing. The computer was sold to Lockheed-Martin for an undisclosed price. It is supercooled, requires 15 kilowatts, and supports APIs in multiple programming environments including Python, Java, C++, SQL, and MATLAB.