Aasemoon'z Cluster

Intel unveiled plans Monday to take supercomputing performance to levels that are orders of magnitude greater than currently possible by the end of the decade. Coincidentally, the news broke just after Japan's K supercomputer had been named the world's fastest, with over three times the processing power as the previous title holder, China's Tianhe-1A system. The power of supercomputers shows no signs of abating. Intel said its new Many Integrated Core (MIC) architecture will deliver exaflop-scale supercomputing by 2018, with the fastest supercomputers reaching up to 4 exaflops of performance by 2020.

In then the past few years we have seen multiprocessing systems become more mainstream, in fact most modern personal computer CPUs now feature symmetric multiprocessing systems (SMP), where multiple instantiations of the same processor share the processing burden of the applications running on the PC. While SMPs are quite common today, we typically have not seen a shift towards multiprocessing in embedded computing. However, a new type of embedded design technique gives engineers the freedom to intelligently distribute processing functions across a digital subsystem. This article will look at an example of the distributed processing technique using Cypress Semiconductor's PSoC 3 and PSoC 5 architectures, which consist of a main CPU (in this case an 8051 or ARM Cortex M3), a DMA engine, and array of Universal Digital Blocks (UDB).

Friday nights on Syfy Channel this past fall wasn’t the only place to get a fix of Stargate Universe. Each week MGM also released new kino webisodes — short scenes that complement the TV show. Some of these are general introductions to the ship and its (reluctant) new crew; others tie in directly to an episode, functioning as something of a deleted scene.

In case you missed them, below you can see all 22 kino webisodes released during the first half of the season! The kino webisodes were directed by Ivon Bartok (friend of the site), with a total of 30 installments to be released during SGU’s first season.

The first part of this white paper explores the basic concepts behind HDMI, the markets it serves and its leadership role in multimedia interfaces. This is followed by a tutorial on the new capabilities of HDMI 1.4 and their role in providing a richer, more straightforward user experience. Next, we'll explore a series of user case scenarios that illustrate how the HEAC feature can simplify cabling requirements between digital home multimedia devices. The last portion of this paper discusses the architectural considerations and technical details involved with incorporating the Ethernet and Sony/Philips Digital Interconnect Format (S/PDIF) standards into the HDMI system-on-chips (SoCs) to support the HEAC feature.

NAMO (Novel Articulated MObile platform)  is a humanoid robot built by The Institute of Field Robotics (FIBO) at King Mongkut’s University of Technology Thonburi in Thailand. FIBO is active in the RoboCup scene and have developed a wide range of robot types, including an experimental biped.  NAMO was unveiled on March 29th 2010, serving as FIBO’s mascot as part of the university’s 50 year anniversary celebrations.  NAMO will be used to welcome people to the university and may be deployed at museums.  Given its friendly appearance and functionality, it could be used to research human robot interaction and communication. NAMO is 130cm (4′3″) tall and has 16 degrees of freedom.  It moves on a stable three-wheeled omnidirectional base, and is equipped with a Blackfin camera for its vision system.  It is capable of simple gesture recognition, visually tracks humans or objects of interest automatically, and can speak a few phrases in a child-like voice (in Thai).

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.

From multicore to many-core to hard-to-describe-in-a-single-word core

The consumer handheld market is growing by leaps and bounds. With more processing power and increased support for more applications, portable products are cross-pollinating with traditional computing systems even as the product life cycle has decreased considerably in this market segment. As a result, especially in this era of economic slowdown, it is imperative that new products meet the time-to-market window to gain maximum acceptance. A decrease in product life cycles requires a reduced development cycle and an increased emphasis on reusability and reprogrammability. The emerging handheld market is also seeing interesting trends in which each individual device in a family has lower volumes but there is more customization across the series of devices, effectively upping the total unit volumes. The key challenge then becomes how to develop a system that is widely reusable and also customizable. These requirements have led designers increasingly to turn to the FPGA for handheld-product development. The FPGA has become more powerful and feature-rich, while gate counts, area and frequency have increased. FPGA development and turnaround cycles are considerably shorter than those of custom ASICs, and the added advantage of reprogrammability can make the FPGA a more compelling solution for handheld embedded systems.

There is a long history of attempts at replicating neural systems either in software or in conventional semiconductors, such as the FACETS project (not to mention the creation of conventional logic gates from lab-grown biological neurons!) According to a USC Viterbi news release, researchers at the BioRC project, whose goal is research on an artificial cortex, have succeeded in creating a functioning synapse from carbon nanotubes. The new research was presented by Alice C. Parker in the paper "A biomimetic fabricated carbon nanotube synapse for prosthetic applications" at the Life Science Systems and Applications Workshop in April 2011. (unfortunately the actual paper is behind a paywall but the abstract is readable). An earlier paper, "A Biomimetic Carbon Nanotube Synapse Circuit", describes the proposed design of synapse including schematics and comparison with biological neural

Researchers at Purdue University have developed two new techniques for computer-vision technology that mimic how humans perceive three-dimensional shapes.The techniques, heat mapping and heat distribution, apply mathematical methods to enable machines to perceive three-dimensional objects by mimicking how humans perceive three-dimensional shapes by instantly recognizing objects no matter how they are twisted or bent, an advance that could help machines see more like people.

Part 5 of an excerpt from the book "Acoustics and Psychoacoustics," fourth edition, begins with a brief look at noise-reducing headphones and "mosquito" units and ringtones, and then delves into the ins and outs of audio coding systems.

Tigal announced the VoiceGP family of products under its VeeaR brand of voice and speech recognition products. The product family consists of the VoiceGP module and two development kits with bundled development software. It combines all the hardware and software required for easy and cost effective development and implementation of speech synthesis and multi-language speaker independent and speaker dependent speech recognition capabilities to virtually any application, says the manufacturer. The VoiceGP Module is based on Sensory's RSC-4128 mixed signal processor. Its 42x72mm footprint and two 28-pin connectors with 2.54mm pin spacing make the module breadboard friendly and suitable for prototype boards.

A new network design that avoids the need to convert optical signals into electrical ones could boost capacity while reducing power consumption.

This article discusses the requirements, constraints and challenges in creating high-quality musical instruments using electronic components (both analog and digital) available today.

A test circuit built with nanowires of silicon could point the way to much smaller transistors, say the IBM researchers who created it. Researchers from IBM’s Thomas J. Watson Research Center announced today at the annual Symposium on VLSI Technology, in Honolulu, that they have built a ring oscillator out of field-effect transistors (FETs) based on nanowires with diameters as small as 3 nanometers. The oscillator—is composed of 25 inverters using negative- and positive-channel FETs. The device, which demonstrated a delay of just 10 picoseconds per stage, shows that engineers can build a working circuit from transistors with much shorter channel lengths than today’s devices. Current flows through an FET’s channel under the control of the device’s gate. Scaling down the channel length will be critical if the dimensions of circuits on silicon chips are to continue to shrink, says Jeffrey Sleight, a senior technical staff member at IBM.

In mathematics, computer science, and related subjects, an 'algorithm' is an effective method for solving a problem expressed as a finite sequence of instructions. Algorithms are used for calculation, data processing, and many other fields. (In more advanced or abstract settings, the instructions do not necessarily constitute a finite sequence, or even a sequence; see, for example, "nondeterministic algorithm".) Each algorithm is a list of well-defined instructions for completing a task. Starting from an initial state, the instructions describe a computation that proceeds through a well-defined series of successive states, eventually terminating in a final ending state. The transition from one state to the next is not necessarily deterministic; some algorithms, known as randomized algorithms, incorporate randomness. [source = Bing Reference]