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DSP options to accelerate your DSP+FPGA design - 0 views

  • Although signal processing is usually associated with digital signal processors, it is becoming increasingly evident that FPGAs are taking over as the platform of choice in the implementation of high-performance, high-precision signal processing. For many such applications, the choice generally boils down to using either a single FPGA, a FPGA with an associated DSP processor or a farm of DSP processors.
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The basics of DSP for use in intelligent sensor applications: Part 3 - 0 views

  • Earlier in this series, we touched on one problem that can arise when sampling an analog signal, namely the problem of aliasing. There are three other issues with signal sampling to which we now turn our attention: digitization effects, finite register length effects, and oversampling. So far, weve assumed that all of the signals were measuring are continuous analog values; i.e., our measurements are completely accurate. Even in the cases in which we have noise, the underlying assumption is that the measurement itself, for example the noisy sensor output voltage, is known precisely.
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TechOnline | Digital Signal Processing: A Practical Guide (Part 4) - 0 views

  • This book is intended for those who work in or provide components for industries that use digital signal processing (DSP). There is a wide variety of industries that utilize this technology. While the engineers who implement applications using DSP must be very familiar with the technology, there are many others who can benefit from a basic knowledge of its' fundamental principals, which is the goal of this book—to provide a basic tutorial on DSP.
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Asymmetric Processing Makes the Most of Multicore Processors « The Embedded Beat - 0 views

  • Let’s face it. Most of the gear you use at work or play has multicore processors in it. Your laptop has them (the CPU itself has two cores, and the dedicated graphics processor has many more). That game console in the living room has still more, and even a high-end smartphone typically has a CPU and graphics core on a single chip. Out of sight but definitely not out of mind–particularly if they cease working–are the servers and high-throughput network routers, all which have numerous multicore processors in them. The multiple cores in these devices work in concert to provide quick responses to user queries or to manage the smooth flow of data throughout the office.
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Opus - Asynchronous Power Efficient DSP Architecture - 0 views

  • Opus is Octasic's high-performing, ultra low-power, asynchronous DSP technology optimized for basestations, video processing and media gateway solutions. Asynchronous designs deliver similar computing performance to synchronous designs, but use less silicon and less power. No clock tree No state-elements Less sensitive to process and temperature variations
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Filter banks, part 2: Optimization and synthesis - 0 views

  • High Level Synthesis Architectural Optimization Basics In part 1 of this article we introduced basic filter bank theory and used the Synplify DSP High Level Synthesis (HLS) tool to implement an example filter bank into three alternative architectures. In part 2 we dive deeper into these three architectures to better understand how these filters work. We will also examine the HLS optimizations we applied and the resulting benefits. Example Filter Bank Review Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample rate (red) has been chosen and the output sample rate is downsampled by 16 (green).
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Virtualization options for embedded multicore systems - 0 views

  • Introduction: The proliferation of multicore processors and the desire to consolidate applications and functionality will push the embedded industry into embracing virtualization in much the same way it has been embraced in the server and compute-centric markets. However, there are many paths to virtualization for embedded systems. After a tour of those options and their pros and cons, Freescale Semiconductor’s Syed Shah shows why the bare metal hypervisor-based approach, coupled with hardware virtualization assists in the core, the memory subsystem and the I/O, offers the best performance.
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Implementing the Viterbi algorithm in modern digital communications systems - 0 views

  • With the consumer demand for richer content and its resultant , increasing high data bandwidth continuing to drive communications systems, coding for error control has become extraordinarily important. One way to improve the bit error rate (BER), while maintaining high data reliability, is to use an error correction technique like the Viterbi algorithm. Originally conceived by Andrew Viterbi as an error-correction scheme for noisy digital communication, the Viterbi algorithm provides an efficient method for forward error correction (FEC) that improves channel reliability. Today, it is used in many digital communications systems in applications as diverse as CDMA and GSM digital cellular, dial-up modems, satellite, deep-space communications and 802.11 wireless LANs. It is also commonly used in speech recognition, keyword spotting and computational linguistics.
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EETimes.com - Ceva launches programmable HD video processor - 0 views

  • DSP core licensor Ceva Inc. is due to unveil a software-programmable multimedia video processor architecture at the Mobile World Congress in Barcelona next week. The multicore architecture, called MM3000, which comes complete with C compilers, power management provision and an RTOS/multithreading scheduler is intended to be able to process any and all video codecs up to the highest resolutions and frame rates currently available as well as future codecs for things like 3-D video.
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TI multicore SoC is a bag of nice ideas | DSP DesignLine - 0 views

  • While the new multicore system on chip (SoC) signal-processing architecture announced by Texas Instruments this week at Mobile World Congress hits all the right notes with respect to what's needed in next-generation basestation designs, it rings a bit hollow given how sketchy the architectural details remain when contrasted with more 'real' announcements from the likes of Freescale. For sure, the requirements of next-generation basestations will push all architectures to their limits and beyond. Balancing lower power and lower cost with increasingly parallel, math-intensive processing to meet multiuser demands for high-data-rate data in 3GPP Long Term Evolution (LTE) Release 8 all-IP networks is not going to be easy, especially with the introduction of MIMO, beam forming, OFDMA and many other enhancements engineered to maximize spectral efficiency.
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    This is pretty kool.....
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Meeting timing specs on boards with picoseconds of margin - 0 views

  • Length-match your traces to within 100 mils. Or is it 10 mils? Or should you go down to 1 mil? Should you include the lengths of the vias? How about the lengths of resistors? Understanding the origin of length-matching requirements, coupled with some rudimentary signal integrity analysis, can help answer these questions.   Determining length requirements requires an understanding of flight time, electrical length vs. physical length, loading and signal quality. Those elements are vital in determining what the length really needs to be, as well as in determining the allowable trade-offs to meet system timing goals.
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Module aids Camera Link FPGA image processing | Industrial Control Designline - 0 views

  • National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing. The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.
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Delta-Sigma converters for audio output in an infotainment FPGA - 0 views

  • Field programmable gate arrays (FPGAs) present an efficient and inexpensive alternative when it comes to implementing complete embedded systems along with important peripheral functions. The reconfigurable logic circuitry of an FPGA offers tremendous flexibility. A lesser known feature is that the outputs of a digital FPGA also permit various analogue applications.
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The importance of frequency stability in electronic musical instruments | Audio DesignLine - 0 views

  • This article discusses the requirements, constraints and challenges in creating high-quality musical instruments using electronic components (both analog and digital) available today.
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Acoustics and Psychoacoustics Applied - Part 5: Audio coding systems and more | Audio D... - 0 views

  • Part 5 of an excerpt from the book "Acoustics and Psychoacoustics," fourth edition, begins with a brief look at noise-reducing headphones and "mosquito" units and ringtones, and then delves into the ins and outs of audio coding systems.
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Signal processing library speeds up video analytics deployment - 0 views

  • Pico Computing has developed a signal processing library which is made up of a set of FPGA firmware components and related tools that speed the development and deployment of advanced video and network analytics for security, defense and aerospace applications.The library, which includes flexible components for signal analysis, feature detection, scale-space generation, correlation and filtering, has been validated and optimized for Pico Computing platforms based on the latest-generation Xilinx Virtex-5 and Virtex-6 FPGA devices.
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Interactive geometric sound propagation - 0 views

  • Realistic sound rendering can directly impact the perceived realism of users of interactive media applications. An accurate acoustic response for a virtual environment is attuned according to the geometric representation of the environment. This response can convey important details about the environment, such as the location and motion of objects. The most common approach to sound rendering is a two-stage process: Sound propagation: the computation of impulse responses (IRs) that represent an acoustic space. Audio rendering: the generation of spatialized audio signal from the impulse responses and dry (anechoically recorded or synthetically generated) source signals.
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Mercury Releases OpenSAL - Open Source Version of Scientific Algorithm Library | Milita... - 0 views

  • CHELMSFORD, MA.  October 7, 2010  Mercury Computer Systems, Inc. (NASDAQ: MRCY, www.mc.com), a trusted ISR subsystems provider, announced the availability of OpenSAL, an open source version of its award-winning Scientific Algorithm Library (SAL) for vector math acceleration. SAL is a high-throughput, low-latency signal processing library containing efficient algorithms with the fewest possible instructions and computing resources. OpenSAL provides a robust API, C code reference design and documentation for over 400 SAL math functions.
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Taking movies beyond Avatar - for under £100 - 1 views

  • A new development in virtual cameras at the University of Abertay Dundee is developing the pioneering work of James Cameron’s blockbuster Avatar using a Nintendo Wii-like motion controller – all for less than £100.Avatar, the highest-grossing film of all time, used several completely new filming techniques to bring to life its ultra-realistic 3D action. Now computer games researchers have found a way of taking those techniques further using home computers and motion controllers.James Cameron invented a new way of filming called Simul-cam, where the image recorded is processed in real-time before it reaches the director’s monitor screen. This allows actors in motion-capture suits to be instantly seen as the blue Na’vi characters, without days spent creating computer-generated images.
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TechOnline | Enabling LTE Development with TI's New Multicore SoC Architecture - 0 views

  • The goal of Long Term Evolution (LTE) is to achieve higher data rates through more efficient transmission, and thus improving the cellular phone user experience by enabling powerful new devices. The changes required in this technology present new challenges for base station vendors and their suppliers. Supporting 4G systems efficiently requires a number of innovations in DSP design; these innovations are moving the industry toward SoC architectures to support such systems. This paper will explore how TI's new architecture enables the key features in 4G systems.
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