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C9 Lectures: Yuri Gurevich - Introduction to Algorithms and Computational Complexity, 1... - 0 views

  • In mathematics, computer science, and related subjects, an 'algorithm' is an effective method for solving a problem expressed as a finite sequence of instructions. Algorithms are used for calculation, data processing, and many other fields. (In more advanced or abstract settings, the instructions do not necessarily constitute a finite sequence, or even a sequence; see, for example, "nondeterministic algorithm".) Each algorithm is a list of well-defined instructions for completing a task. Starting from an initial state, the instructions describe a computation that proceeds through a well-defined series of successive states, eventually terminating in a final ending state. The transition from one state to the next is not necessarily deterministic; some algorithms, known as randomized algorithms, incorporate randomness. [source = Bing Reference]
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Embedded.com - Early verification cuts design time & cost in algorithm-intensive systems - 1 views

  • Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.
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Implementing the Viterbi algorithm in modern digital communications systems - 0 views

  • With the consumer demand for richer content and its resultant , increasing high data bandwidth continuing to drive communications systems, coding for error control has become extraordinarily important. One way to improve the bit error rate (BER), while maintaining high data reliability, is to use an error correction technique like the Viterbi algorithm. Originally conceived by Andrew Viterbi as an error-correction scheme for noisy digital communication, the Viterbi algorithm provides an efficient method for forward error correction (FEC) that improves channel reliability. Today, it is used in many digital communications systems in applications as diverse as CDMA and GSM digital cellular, dial-up modems, satellite, deep-space communications and 802.11 wireless LANs. It is also commonly used in speech recognition, keyword spotting and computational linguistics.
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Mercury Releases OpenSAL - Open Source Version of Scientific Algorithm Library | Milita... - 0 views

  • CHELMSFORD, MA.  October 7, 2010  Mercury Computer Systems, Inc. (NASDAQ: MRCY, www.mc.com), a trusted ISR subsystems provider, announced the availability of OpenSAL, an open source version of its award-winning Scientific Algorithm Library (SAL) for vector math acceleration. SAL is a high-throughput, low-latency signal processing library containing efficient algorithms with the fewest possible instructions and computing resources. OpenSAL provides a robust API, C code reference design and documentation for over 400 SAL math functions.
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Module aids Camera Link FPGA image processing | Industrial Control Designline - 0 views

  • National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing. The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.
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Autonomous Satellite Chasers Can Use Robotic Vision to Capture Orbiting Satellites | Po... - 0 views

  • UC3M's ASIROV Robotic Satellite Chaser Prototype ASIROV, the Acoplamiento y Agarre de Satélites mediante Sistemas Robóticos basado en Visión (Docking and Capture of Satellites through computer vision) would use computer vision tech to autonomously chase down satellites in orbit for repair or removal. Image courtesy of Universidad Carlos III de Madrid Spanish robotics engineers have devised a new weapon in the battle against zombie-sats and space junk: an automated robotics system that employs computer vision technology and algorithmic wizardry to allow unmanned space vehicles to autonomously chase down, capture, and even repair satellites in orbit. Scientists at the Universidad Carlos III de Madrid (UC3M) created the system to allow for the removal of rogue satellites from low earth orbit or the maintenance of satellites that are nearing the ends of their lives, prolonging their service (and extending the value of large investments in satellite tech). Through a complex set of algorithms, space vehicles known as “chasers” could be placed into orbit with the mission of policing LEO, chasing down satellites that are damaged or have gone “zombie” and dealing with them appropriately.
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IEEE Spectrum: A New Algorithm to Attack Art Fraud - 0 views

  • Every few years, we're wowed by news of some jaw-dropping sum paid for a previously unknown painting or drawing by a famous artist. But how can a buyer truly be sure that a piece is a legitimate creation of, say, Leonardo or Gauguin? Mathematicians at Dartmouth College, in Hanover, N.H., may have the answer. They recently presented a computer-based statistical analysis technique which they say will help art historians and conservators discover even the most skilled forgery. Their method, called sparse coding, learns what characterizes the artist's style at a level of detail that is practically imperceptible to the eye of even the most experienced appraiser. It works by examining small patches of a picture and breaking them down to a set of essential elements.
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robots.net - Physics-based Planning - 0 views

  • Later this month, Carnegie Mellon's CMDragons small-size robotic soccer team will be competing again at RoboCup, to be held in Singapore. CMDragons has tended to find their edge in their software as opposed to their hardware. Their latest software advantage will be their new "physics-based planning", using physics to decide how to move and turn with the ball in order to maintain control. Previous control strategies simply planned where the robot should move to and shoot from, assuming a ball placed at the front center of the dribbler bar would stay there. The goal of Robocup is to create a humanoid robotic soccer team to compete against human players in 2050. Manuela Veloso, the professor who leads the Carnegie Mellon robotic soccer lab, "believe[s] that the physics-based planning algorithm is a particularly noteworthy accomplishment" that will take the effort one step closer to the collective goal.
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Embedded.com - Protecting FPGAs from power analysis security vulnerabilities - 0 views

  • Recent advances in the size and performance of FPGAs, coupled with advantages in time-to-market, field-reconfigurability and lower up-front costs, make FPGAs ideally suited to a wide range of commercial and defense applications [6]. In addition, FPGAs generality and reconfigurability provide important protections against the introduction of Trojan horses during semiconductor manufacturing process[8]. As a result, FPGA applications increasingly involve highly-sensitive intellectual property and trade-secrets, as well as cryptographic keys and algorithms [7].
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TechOnline | FPGA Design Methods for Fast Turn Around - 0 views

  • Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate mark. With designs of this magnitude, the need for fast flows has never been greater. At the same time, designers are seeking rapid feedback on their ASIC or FPGA designs by implementing quick prototypes or initial designs on FPGA-based boards. These prototypes or designs allow designers to start development, verification and debug of the design—in the context of system software and hardware—and also to fine tune algorithms in the design architecture. Quick and intuitive debug iterations to incorporate fixes are of great value. The ability to perform design updates that don't completely uproot all parts of the design that have already been verified is also a bonus! Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.
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・e-nuvo HUMANOID - 0 views

  • The Nippon Institute of Technology, with Harada Vehicle Design, ZMP, and ZNUG Design, have developed a humanoid robot about the size of an elementary school student for educational purposes.  The university adopted 35 of ZMP’s e-nuvo WALK robots in 2004 for a 1:1 student-robot ratio.  Whereas the e-nuvo WALK (the educational version of NUVO) is quite small, the new robot is tall enough to interact with its environment in a more meaningful way.  Students will demonstrate the robot at elementary and junior high schools, as well as care facilities.  The goal is to improve student learning by raising awareness of bipedal robot technology and its connection to math and physics, while also giving them hands-on experience with the bot.  Additionally, by visiting care facilities the university students will come to understand the real-world needs and applications for robots.
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    The Nippon Institute of Technology, with Harada Vehicle Design, ZMP, and ZNUG Design, have developed a humanoid robot about the size of an elementary school student for educational purposes.  The university adopted 35 of ZMP's e-nuvo WALK robots in 2004 for a 1:1 student-robot ratio.  Whereas the e-nuvo WALK (the educational version of NUVO) is quite small, the new robot is tall enough to interact with its environment in a more meaningful way.  Students will demonstrate the robot at elementary and junior high schools, as well as care facilities.  The goal is to improve student learning by raising awareness of bipedal robot technology and its connection to math and physics, while also giving them hands-on experience with the bot.  Additionally, by visiting care facilities the university students will come to understand the real-world needs and applications for robots.\nThe e-nuvo HUMANOID stands 126cm (4′) tall and weighs 15kg (33 lbs), with 21 degrees of freedom (2 legs x6, 2 arms x3, head x3), powered by a Lithium Ion battery.  It is equipped with the usual sensors including cameras, accelerometers, gyro sensors, obstacle detection sensors, distance sensors, and peizoelectric sensors, and can be controlled via PC or remote controller.  Besides basic speech capabilities, the robot can serve as a kind of teacher's assistant, since it has a built-in projector which will allow it to display diagrams on a blackboard that might be difficult to explain in words alone.  The robot will be programmed using Microsoft Robotics Developer Studio, which the students have been using to test control algorithms for the e-nuvo WALK robots
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PRODUCT HOW TO - Embedding multicore PCs for Robotics & Industrial Control | Industrial... - 0 views

  • PC-compatible industrial computers are increasing in computing power at a rapid rate due to the availability of multi-core microprocessor chips, and Microsoft Windows has become the de-facto software platform for implementing human-machine interfaces (HMIs). PCs are also becoming more reliable. With these trends, the practice of building robotic systems as complex multi-architecture, multi-platform systems is being challenged. It is now becoming possible to integrate all the functions of machine control and HMI into a single platform, without sacrificing performance and reliability of processing. Through new developments in software, we are seeing industrial systems evolving to better integrate Windows with real-time functionality such as machine vision and motion control. Software support to simplify motion control algorithm implementation already exists for the Intel processor architecture.
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TechOnline | FPGA Design Methods for Fast Turn Around - 0 views

  • Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate mark. With designs of this magnitude, the need for fast flows has never been greater. At the same time, designers are seeking rapid feedback on their ASIC or FPGA designs by implementing quick prototypes or initial designs on FPGA-based boards. These prototypes or designs allow designers to start development, verification and debug of the design—in the context of system software and hardware—and also to fine tune algorithms in the design architecture. Quick and intuitive debug iterations to incorporate fixes are of great value. The ability to perform design updates that don't completely uproot all parts of the design that have already been verified is also a bonus! Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.
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Recipe for Efficiency: Principles of Power-Aware Computing | April 2010 | Communication... - 0 views

  • Power and energy are key design considerations across a spectrum of computing solutions, from supercomputers and data centers to handheld phones and other mobile computers. A large body of work focuses on managing power and improving energy efficiency. While prior work is easily summarized in two words—"Avoid waste!"—the challenge is figuring out where and why waste happens and determining how to avoid it. In this article, I discuss how, at a general level, many inefficiencies, or waste, stem from the inherent way system architects address the complex trade-offs in the system-design process. I discuss common design practices that lead to power inefficiencies in typical systems and provide an intuitive categorization of high-level approaches to addressing them. The goal is to provide practitioners—whether in systems, packaging, algorithms, user interfaces, or databases—a set of tools, or "recipes," to systematically reason about and optimize power in their respective domains.
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InfoQ: A Pattern Language for Parallel Programming - 0 views

  • Ralph Johnson presents a pattern language that he and his colleagues are working on in an attempt to solve the hard issues of parallel programming through a set of design patterns: Structural Patterns, Computational Patterns, Parallel Algorithm Strategy Patterns, Implementation Strategy Patterns, and Concurrent Execution Patterns.
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Don Syme's WebLog on F# and Related Topics : F# 2.0 Released - 0 views

  • Today sees the launch of Visual Studio 2010, at five launch events around the world, as announced by Bob Muglia, Jason Zander and S. Somasegar, and presented live today in Las Vegas.   Visual Studio 2010 includes the official version 2.0 of the F# language. As is our custom on the F# team, we also release a matching MSI and ZIP of F# 2.0 (for use with Visual Studio 2008 and as a standalone compiler on a range of platforms)   Today represents the culmination of 7 years of work on the language at Microsoft Research, and, more recently, the Microsoft Developer Division. I am immensely proud of what we’ve achieved. F# brings a productive functional and object-oriented programming language to .NET, extending the platform to new audiences in technical, algorithmic, data-rich, parallel and explorative domains, and its inclusion in Visual Studio 2010 represents a huge milestone for the language.   To help understand what we’re doing with F#, I’ve listed some of the common questions people have about the language below.  We thank everyone who has been involved in the production of F#, especially the many users who have given us feedback on the language!
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TechOnline | Study of Model Based Etch Bias Retarget for OPC - 0 views

  • Model based Optical proximity correction is usually used to compensate for the pattern distortion during the microlithography process. Currently, almost all the lithography effects, such as the proximity effects from the limited NA, the 3D mask effects due to the shrinking critical dimension, the photo resist effects, and some other well known physical process, can all be well considered into modeling with the OPC algorithm. However, the micro-lithography is not the final step of the pattern transformation procedure from the mask to the wafer. The etch process is also a very important stage. It is well known that till now, the etch process still can't be well explained by physics theory. In this paper, we will demonstrate our study on the model based etch bias retarget for OPC.
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Algorithmic delay and synchronization in MPEG audio codecs | Audio DesignLine - 0 views

  • A variety of audio compression technologies are being used today, each having a distinct advantage over the other in terms of compression ratio, coding delay, coding complexity or legacy system compatibility. This makes subset of audio codecs suited for particular systems and makes working with multiple audio compression technologies indispensable. In designing time-critical systems like conferencing, broadcast transcoding systems or be it in designing any audio and video play-out system, the knowledge of the delay encountered while audio encoding or decoding becomes critical.
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Doing C-code generation better: from graphical code to embedded target | Industrial Con... - 0 views

  • One challenge designers face is the need to translate their algorithms into code for use in embedded targets. The task has proven to be long and prone to error. This article examines how the use of high-level design tools and C code generation capabilities improves the design flow by exploring different use cases and how to reduce the amount of embedded technology expertise required to program embedded targets.
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Try F# - 0 views

  • F# is ideal for data-rich, concurrent and algorithmic development: "simple code to solve complex problems". F# is a simple and pragmatic programming language combining functional, object-oriented and scripting programming, and supports cross-platform environments including PC, Mac, and Linux. We'll provide the tutorials, resources and tools you’ll need to begin working with F# right away.
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