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IEEE Spectrum: Flexible Flash - 0 views

  • 4 January 2010—Though flexible devices such as roll-up displays have been promised for several years, their commercialization has been stalled by a missing ingredient: a flexible form of flash memory. But researchers at the University of Tokyo have recently developed an organic, floating-gate nonvolatile memory that behaves like flash memory, which may solve that problem. While silicon-based flash memory is fine for the mass data storage found in cellphones, digital music players, and thumb drives, fabricating it requires high processing temperatures, thus ruling out its production on flexible substrates like plastic. Organic semiconductors, however, can be processed at temperatures well below the melting point of most plastics. What's more, "the cost of flash memory is too high to use in applications that require large arrays of memory," says Tsuyoshi Sekitani, an assistant professor in the University of Tokyo's department of electrical and electronic engineering and one of the researchers who developed the new memory. "But we can print our organic memory on flexible substrates and over large areas using inkjet printers. So costs will be low."
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Observations: Surprised? How the brain records memories of the unexpected - 0 views

  • Remember the last time that something a friend did caught you off guard? Probably—and that's because the human brain is specially tuned to remember things that are out of the ordinary. But just how the brain treats those instances has remained uncertain. Some scientists had hypothesized that an unexpected stimulus would trigger a loop that involved both the hippocampus (responsible in part for long-term memory) and nucleus accumbens (involved in reward and pleasure) to make those memories super sticky. But without peering into these centers, researchers could not know for sure.
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Implementing custom DDR and DDR2 SDRAM external memory interfaces | Programmable Logic ... - 0 views

  • The FPGAs referenced in these articles have complex dedicated I/O circuitries that are primarily designed to support external memory interfaces. The ALTMEMPHY megafunction is designed to support the most common memory standards, such as the DDR and DDR 2 SDRAM and QDR II+/QDR II SRAM (in a burst length of 4) interfaces. The ALTMEMPHY megafunction should be used whenever possible as it is beneficial to use the IP and timing closure methodologies used with these FPGAs, which enables users not to have to create this function manually as compared with using the ALTDLL and ALTDQ_DQS solution. However, the ALTMEMPHY megafunction does not support other external memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2) or customized DDR and DDR 2 SDRAM external memory standards. For these scenarios, use the ALTDLL and ALTDQ_DQS megafunctions to access the FPGA architecture and build a custom external memory interface.
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Implementing custom DDR and DDR2 SDRAM external memory interfaces | Programmable Logic ... - 0 views

  • FPGAs referenced in this article have complex dedicated I/O circuitries that are primarily designed to support EMIF. The ALTMEMPHY megafunction is designed to support the most common memory standards, such as the DDR , DDR2 SDRAM, and QDR II+/QDR II SRAM (in a burst length of 4) interfaces. Other external memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2), or customized DDR and DDR 2 SDRAM external memory standards are not supported. Instead, the ALTDLL and ALTDQ_DQS megafunctions are used to access the FPGA architecture and build a custom EMIF.
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Artificial hippocampal system restores long-term memory, enhances cognition | KurzweilAI - 0 views

  • Theodore Berger and his team at the USC Viterbi School of Engineering’s Department of Biomedical Engineering have developed a neural prosthesis for rats that is able to restore their ability to form long-term memories after they had been pharmacologically blocked.In a dramatic demonstration, Berger blocked the ability to rats to form long-term memories by using pharmacological agents to disrupt the neural circuitry that communicates between two subregions of the hippocampus, CA1 and CA3, which interact to create long-term memory, prior research has shown.
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IEEE Spectrum: Flexible Graphene Memristors - 1 views

  • South Korean researchers have recently made a flexible nonvolatile memory based on memristors—fundamental electronic circuit elements discovered in 2008—using thin graphene oxide films. Memristors promise a new type of dense, cheap, and low-power memory and have typically been made using metal oxide thin films. The new graphene oxide devices should be cheaper and simpler to fabricate—they could be printed on rolls of plastic sheets and used in plastic RFID tags or in the wearable electronics of the future. "We think graphene oxide can be a good candidate for next-generation memory," says Sung-Yool Choi, who leads flexible devices research at the Electronics and Telecommunications Research Institute in Daejeon, South Korea. Choi and his colleagues reported their device last week in Nano Letters.
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Embedded OS - Multi-Core OS | Your Electronics Open Source - 0 views

  • Most multiprocessing systems can be classified as either symmetric multiprocessing (SMP) or asymmetric multiprocessing (AMP). AMP involves the use of interprocessor communication to combine the efforts of multiple processors, each with its own local operating system and hardware resources. Also, AMP involves less OS overhead for each individual processor and a more traditional execution environment for applications. AMP seems like distributed system. The number of peripherals that are supported in today's multicore processors is quickly increasing. Symmetric-multiprocessing (SMP) software is expected to be quickly available to support these peripherals. Basically any OS can be ported to a SMP platform, but the developers must take care of following issues for SMP OS. - Handling of task priority or implicit synchronization - Spinlocks and synchronization - Synchronization between tasks sharing memory - Synchronization between tasks and ISRs sharing memory - Synchronization between ISRs sharing memory
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Josephmallozzi's Weblog - 0 views

  • May 13, 2011: Okay, try to keep up! The Transporter Team! Dark Matter Ship Designs! Movement on the Anime Front! Stargate: SG-1 Season 6 Memories! Notes on Network Notes! And I Answer Your Stargate Questions!
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Amazon Web Services Blog: AWS For High Performance Cloud Computing - NASA, MATLAB - 0 views

  • The MATLAB team at MathWorks tested performance scaling of the backslash ("\") matrix division operator to solve for x in the equation A*x = b. In their testing, matrix A occupies far more memory (290 GB) than is available in a single high-end desktop machine—typically a quad core processor with 4-8 GB of RAM, supplying approximately 20 Gigaflops. Therefore, they spread the calculation across machines. In order to solve linear systems of equations they need to be able to access all of the elements of the array even when the array is spread across multiple machines. This problem requires significant amounts of network communication, memory access, and CPU power. They scaled up to a cluster in EC2, giving them the ability to work with larger arrays and to perform calculations at up to 1.3 Teraflops, a 60X improvement. They were able to do this without making any changes to the application code. Here's a graph showing the near-linear scalability of an EC2 cluster across a range of matrix sizes with corresponding increases in cluster size for MATLAB's parallel backslash operator:
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Five Tips for Improving IntelliJ IDEA Performance | geek listed - 0 views

shared by Aasemoon =) on 02 Jan 10 - Cached
  •  
    Since I totally luv IDEA...... "We use JetBrains IntelliJ IDEA Java IDE and love its features, functionality, and price point. Dealing with its performance is another matter, however. When developing Seam 2.x applications, IDEA can just crawl - and this is when sticking to just one project or SVN branch at a time. Some of the biggest performance hits our team has noticed are: 1. File indexing on IDEA startup 2. Long code completion times when editing XHTML/JSF files 3. Pauses when switching from one Java or XHTML file to another 4. Calls to Ant targets can drag on forever for no apparent reason while others time they are tidy and fast Here is a collection of ideas on how to improve the performance of IDEA; note that not all of these will be applicable to your environment or application. For example, we wouldn't consider turning off local history options as this is invaluable. 1. If you're not using Subversion or other version control system, turn off synchronized files. This can be disabled from the Settings -> General, and disabling "Synchronize Files on Frame Activation". 2. Revert to IDEA's original visual interface. Browse to Settings -> Appearance and select the "IDEA 4.5 Default" theme. 3. Decrease the size of local history of code changes. Even if you find this feature invaluable, you can still improve performance of IDEA by reducing the number of days of local history IDEA will store. By default this option is set to three days! 4. Disable unused plugins. You mean you're not developing GWT apps and you're not working with JetGroovy? Great, then why not disable some of those plugins? 5. Increase the IDEA Java VM heap size. I can attest to this offering much improved performance; if you can spare the memory, follow these directions: 1. locate your Program Files/JetBrains/IDEA x.x/bin directory 2. open idea.exe.vmoptions 3. modify Xms, Xmx, and XX:MaxPermSize settings as needed"
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IEEE Spectrum: Design Challenges Loom for 3-D Chips - 0 views

  • Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them. "There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec. On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.
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Dr Dobbs - Memory Management as a Separate Thread - 0 views

  • Researchers at North Carolina State University have developed a new approach to software development that will allow common computer programs to run up to 20 percent faster and possibly incorporate new security measures. The researchers have found a way to run different parts of some hard-to-parallelize programs — such as word processors and web browsers — at the same time, which makes the programs operate more efficiently.
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Physicists Bring Silicon Chips Closer to Performing All-Optical Computing - 0 views

  • An all-optical integrator, or lightwave capacitor, is a fundamental building block equivalent to those used in multi-functional electronic circuits. Associate Professor David Moss, a senior researcher within the Institute for Photonic and Optical Science (IPOS), leads an international team which has developed the optical integrator on a CMOS compatible silicon chip. The device, a photonic chip compatible with electronic technology (CMOS), will be a key enabler of next generation fully-integrated ultrafast optical data processing technologies for many applications including ultra-fast optical information-processing, optical memory, measurement, computing systems, and real-time differential equation computing units.
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| Programmable Logic DesignLine - 0 views

  • Menta SAS and LIRMM have taped out what they believe is the of worlds first MRAM-based FPGA which has patent-protected circuitry enabling compact integration of MRAM and embedded-FPGA solutions. Researchers at the Montpellier Laboratory of Informatics, Robotics and Microelectronics (LIRMM), in France, claimed in October that they had developed a FPGA circuit based on non volatile resistive memory cell.
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Virtualization options for embedded multicore systems - 0 views

  • Introduction: The proliferation of multicore processors and the desire to consolidate applications and functionality will push the embedded industry into embracing virtualization in much the same way it has been embraced in the server and compute-centric markets. However, there are many paths to virtualization for embedded systems. After a tour of those options and their pros and cons, Freescale Semiconductor’s Syed Shah shows why the bare metal hypervisor-based approach, coupled with hardware virtualization assists in the core, the memory subsystem and the I/O, offers the best performance.
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Joe Duffy: A (brief) retrospective on transactional memory | Lambda the Ultimate - 0 views

  • In short, Joe argues, "Throughout, it became abundantly clear that TM, much like generics, was a systemic and platform-wide technology shift. It didn’t require type theory, but the road ahead sure wasn’t going to be easy." The whole blog post deals with how many implementation challenges platform-wide support for STM would be in .NET, including what options were considered. He does not mention Maurice Herlihy's SXM library approach, but refers to Tim Harris's work several times.
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The Ultimate Connection Machine | h+ Magazine - 1 views

  • Tilikum the killer whale (Orcinus orca) made news recently in the tragic death of his Sea World trainer, Dawn Brancheau. Tilikum pulled Brancheau into the water when he grabbed her floating ponytail — much like a cat might grab yarn attached to a stick. Complex play behavior is a sign of intelligence, but unfortunately little is known of the circuitry of even a cat’s brain, much less the massive brain of an orca — roughly four times the size of a human brain. See Also The Race to Reverse Engineer the Human Brain Ray Kurzweil Interview Brain on a Chip MIT neuroscientists are developing computerized techniques to map the millions of miles of neuronal circuits in the brain that may one day shed some light on the differences between Homo sapiens sapiens and other species, and will likely clarify how those neurons give rise to intelligence, personality, and memory. Developing connectomes (maps of neurons and synapses) may have just as much impact as sequencing the human genome. Here’s a video showing 3D rotating nodes and edges in a small connectome:
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DNA-assisted solution processing for high-performance thin-film transistors - 0 views

  • Single-walled carbon nanotube (SWCNT)-based thin film transistors (TFTs) could be at the core of next-generation flexible electronics – displays, electronic circuits, sensors, memory chips, and other applications that are transitioning from rigid substrates, such as silicon and glass, to flexible substrates. What's holding back commercial applications is that industrial-type manufacturing of large scale SWCNT-based nanoelectronic devices isn't practical yet because controlling the morphology of single-walled carbon nanotubes is still causing headaches for materials engineers.
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What next for microcontrollers? - 0 views

  • The embedded world is constantly changing. You might not have noticed, but if you take a minute to recall what a microcontroller system was like 10 years ago and compare it to today's latest microcontroller systems, you will find that PCB design, component packages, level of integration, clock speed, and memory size have all going through several generations of change. One of the hottest topics in this area is when will the last of remaining 8-bit microcontroller users start to move away from legacy architectures and move to modern 32-bit processor architectures like the ARM Cortex-M based microcontroller family. Over the last few years there has been a strong momentum of embedded developers starting the migration to 32-bit microcontrollers and, in this multi-part article, we will take a look at some of the factors accelerating this migration.
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Leveraging FPGA and CPLD digital logic to implement analog to digital converters - 0 views

  • Ted Marena of Lattice Semiconductor Corp., points out that designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function components on their printed circuit board. In addition to these digital functions, FPGAs and CPLDs can also implement common analog functions using an LVDS input, a simple resistor capacitor (RC) circuit and some FPGA or CPLD digital logic elements to create an analog to digital converter (ADC).
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