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Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them. "There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec. On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.

The marriage of high performance optics with microfluidics could prove the perfect match for making lab-on-a-chip technologies more practical. Microfluidics, the ability to manipulate tiny volumes of liquid, is at the heart of many lab-on-a-chip devices. Such platforms can automatically mix and filter chemicals, making them ideal for disease detection and environmental sensing. The performance of these devices, however, is typically inferior to larger scale laboratory equipment. While lab-on-a-chip systems can deliver and manipulate millions of liquid drops, there is not an equally scalable and efficient way to detect the activity, such as biological reactions, within the drops.

An all-optical integrator, or lightwave capacitor, is a fundamental building block equivalent to those used in multi-functional electronic circuits. Associate Professor David Moss, a senior researcher within the Institute for Photonic and Optical Science (IPOS), leads an international team which has developed the optical integrator on a CMOS compatible silicon chip. The device, a photonic chip compatible with electronic technology (CMOS), will be a key enabler of next generation fully-integrated ultrafast optical data processing technologies for many applications including ultra-fast optical information-processing, optical memory, measurement, computing systems, and real-time differential equation computing units.

A new chink has been found in the cryptographic armor that protects bank transactions, credit-card payments, and other secure Internet traffic. And although programmers have devised a patch for it, clever hackers might still be able to break through. The hack, presented in March at a computer security conference in Dresden, Germany, involves lowering the input voltage on a computer’s cryptography chip set and collecting the errors that leak out when the power-starved chips try and (sometimes) fail to encode messages. Crooks would then use those errors to reconstruct the secret key on which the encryption is based. More important, say the hack’s creators, the same attack could also be performed from afar on stressed systems, such as computer motherboards that run too hot or Web servers that run too fast.

Researchers at Purdue University have developed a new design employing carbon nanotubes and small copper spheres that wicks water passively towards hot electronics that could meet the challenges brought on by increasing frequency speeds in chips. The problem of overheating electronics is well-documented and in the past the issue has been addressed with bigger and bigger fans. But with chip features shrinking below 50 nanometers the fan solution is just not cutting it. The Purdue researchers, led by Suresh V. Garimella, came up with a design that uses water as the coolant liquid and transfers the water to an ultrathin thermal ground plane. The design naturally pushes the water through obviating the need for a pump and through the use of microfluidic design is able to boil the water fully, which allows the wicking away of more heat.

Tilikum the killer whale (Orcinus orca) made news recently in the tragic death of his Sea World trainer, Dawn Brancheau. Tilikum pulled Brancheau into the water when he grabbed her floating ponytail — much like a cat might grab yarn attached to a stick. Complex play behavior is a sign of intelligence, but unfortunately little is known of the circuitry of even a cat’s brain, much less the massive brain of an orca — roughly four times the size of a human brain. See Also The Race to Reverse Engineer the Human Brain Ray Kurzweil Interview Brain on a Chip MIT neuroscientists are developing computerized techniques to map the millions of miles of neuronal circuits in the brain that may one day shed some light on the differences between Homo sapiens sapiens and other species, and will likely clarify how those neurons give rise to intelligence, personality, and memory. Developing connectomes (maps of neurons and synapses) may have just as much impact as sequencing the human genome. Here’s a video showing 3D rotating nodes and edges in a small connectome:

At three separate industry events last week, engineers said they are gearing up to deliver in 2011 chips that can handle serial data streams running at 25 Gbits/second to drive next-generation 100 and 400 Gbit/second networks. But they say it's still a mystery how—or if—they can deliver follow-on components for the terabit networks today's Internet data centers are already demanding. The kinds of jobs required to run today's Web 2.0 services such as Google and Facebook can completely overwhelm current 10 Gbit/s Ethernet links in the warehouse-sized data centers those companies use. Such data centers could use hundreds of 100 Gbit/s Ethernet links today, although standards for such networks are still being completed.

While the new multicore system on chip (SoC) signal-processing architecture announced by Texas Instruments this week at Mobile World Congress hits all the right notes with respect to what's needed in next-generation basestation designs, it rings a bit hollow given how sketchy the architectural details remain when contrasted with more 'real' announcements from the likes of Freescale. For sure, the requirements of next-generation basestations will push all architectures to their limits and beyond. Balancing lower power and lower cost with increasingly parallel, math-intensive processing to meet multiuser demands for high-data-rate data in 3GPP Long Term Evolution (LTE) Release 8 all-IP networks is not going to be easy, especially with the introduction of MIMO, beam forming, OFDMA and many other enhancements engineered to maximize spectral efficiency.

Just as photographic film was mostly replaced by silicon image chips, now quantum film threats to replace the conventional CMOS image sensors in digital cameras. Made from materials similar to conventional film—a polymer with embedded particles—instead of silver grains like photographic film the embedded particles are quantum dots. Quantum films can image scenes with more pixel resolution, according to their inventors, InVisage Inc., offering four-times better sensitivity for ultra-high resolution sensors that are cheaper to manufacture.

I remember when, a decade ago, Kevin Warwick, a professor at the University of Reading, in the U.K., implanted a radio chip in his own arm. The feat caused quite a stir. The implant allowed him to operate doors, lights, and computers without touching anything. On a second version of the project he could even control an electric wheelchair and produce artificial sensations in his brain using the implanted chip. Warwick had become, in his own words, a cyborg. The idea of a cyborg -- a human-machine hybrid -- is common in science fiction and although the term dates back to the 1960s it still generates a lot of curiosity. I often hear people asking, When will we become cyborgs? When will humans and machines merge? Although some researchers might have specific time frames in mind, I think a better answer is: It's already happening. When we look back at the history of technology, we tend to see distinct periods -- before the PC and after the PC, before the Internet and after the Internet, and so forth -- but in reality most technological advances unfold slowly and gradually. That's particularly true with the technologies that are allowing us to modify and enhance our bodies.

A test circuit built with nanowires of silicon could point the way to much smaller transistors, say the IBM researchers who created it. Researchers from IBM’s Thomas J. Watson Research Center announced today at the annual Symposium on VLSI Technology, in Honolulu, that they have built a ring oscillator out of field-effect transistors (FETs) based on nanowires with diameters as small as 3 nanometers. The oscillator—is composed of 25 inverters using negative- and positive-channel FETs. The device, which demonstrated a delay of just 10 picoseconds per stage, shows that engineers can build a working circuit from transistors with much shorter channel lengths than today’s devices. Current flows through an FET’s channel under the control of the device’s gate. Scaling down the channel length will be critical if the dimensions of circuits on silicon chips are to continue to shrink, says Jeffrey Sleight, a senior technical staff member at IBM.

It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements.  Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.

Introduction: The proliferation of multicore processors and the desire to consolidate applications and functionality will push the embedded industry into embracing virtualization in much the same way it has been embraced in the server and compute-centric markets. However, there are many paths to virtualization for embedded systems. After a tour of those options and their pros and cons, Freescale Semiconductor’s Syed Shah shows why the bare metal hypervisor-based approach, coupled with hardware virtualization assists in the core, the memory subsystem and the I/O, offers the best performance.

Scientists at the Johns Hopkins University Applied Physics Laboratory (APL) were awarded no less than $34.5 million by the Defense Advanced Research Projects Agency (DARPA) to continue their outstanding work in the field of prosthetic limb testing, which has seen them come up with the most advanced model yet. Their Modular Prosthetic Limb (MPL) system is just about ready to be tested on human subjects, as it has proved successful with monkeys. Basically, the prosthetic arm is controlled by the brain through micro-arrays that are implanted (gently) in the head. They record brain signals and send the commands to the computer software that controls the arm. To be honest, it will be interesting to see just how these hair-chips are attached to the brain, but the APL say clinical tests have shown the devices to be entirely harmless. The monkeys didn’t mind them too much, at least.

Single-walled carbon nanotube (SWCNT)-based thin film transistors (TFTs) could be at the core of next-generation flexible electronics – displays, electronic circuits, sensors, memory chips, and other applications that are transitioning from rigid substrates, such as silicon and glass, to flexible substrates. What's holding back commercial applications is that industrial-type manufacturing of large scale SWCNT-based nanoelectronic devices isn't practical yet because controlling the morphology of single-walled carbon nanotubes is still causing headaches for materials engineers.

PC-compatible industrial computers are increasing in computing power at a rapid rate due to the availability of multi-core microprocessor chips, and Microsoft Windows has become the de-facto software platform for implementing human-machine interfaces (HMIs). PCs are also becoming more reliable. With these trends, the practice of building robotic systems as complex multi-architecture, multi-platform systems is being challenged. It is now becoming possible to integrate all the functions of machine control and HMI into a single platform, without sacrificing performance and reliability of processing. Through new developments in software, we are seeing industrial systems evolving to better integrate Windows with real-time functionality such as machine vision and motion control. Software support to simplify motion control algorithm implementation already exists for the Intel processor architecture.

In case you haven’t realized it, the new trend in computer chip technology is multi-core. This is where most of the speed improvements moving forward will come from on our computers. To take full advantage of this however it is necessary to design your applications using Parallel Programming practices, also known as "parallelism". In today’s episode, we will meet with Stephen Toub, who will share with us some of the overarching concepts associated with parallelism, and some of the ways we are trying to empower developers to develop applications to take advantage of it.

The first part of this white paper explores the basic concepts behind HDMI, the markets it serves and its leadership role in multimedia interfaces. This is followed by a tutorial on the new capabilities of HDMI 1.4 and their role in providing a richer, more straightforward user experience. Next, we'll explore a series of user case scenarios that illustrate how the HEAC feature can simplify cabling requirements between digital home multimedia devices. The last portion of this paper discusses the architectural considerations and technical details involved with incorporating the Ethernet and Sony/Philips Digital Interconnect Format (S/PDIF) standards into the HDMI system-on-chips (SoCs) to support the HEAC feature.

Cypress Semiconductor Corp. has launched a programmable product for data communication over existing power lines. The Powerline Communication product leverages the programmable analog and digital resources of Cypress's PSoC programmable system-on-a-chip architecture. It integrates multiple functions beyond communication, such as power measurement, system management and LCD drive. In addition to its flexibility and integration, the product offers greater than 97% packet success rates without retries and 100% success rates with retries built into the solution's coding, according to Cypress. It also offers the flexibility to communicate over high-voltage and low-voltage power lines for lighting and industrial control, home automation, automatic meter reading and smart energy management applications.