Electronic Everything!

Tiny semiconductor dots could lead to a new type of circuit based on magnetism rather than current flow. At least that’s the hope of researchers who’ve made the dots and are hoping to build them into a workable device. ”We want to make it into a so-called nonvolatile transistor,” says Kang Wang, head of the Device Research Laboratory at the University of California, Los Angeles. Such a ”spintronic” transistor would retain its logic state in the absence of current and require less power to switch a bit, reducing the electrical power required by a computer chip by as much as 99 percent. Wang’s research, supported in part by Intel, was published in March in the online version of Nature Materials. Where electronic transistors rely on the presence or absence of current to register the ones and zeros of digital logic, spintronic transistors depend on ”spin,” a quantum characteristic of the electron. Picture the electron as a rotating globe. When the north pole is pointing upward, that’s spin up; when pointing the other way, it’s spin down. When the spins of most electrons are aligned, the material is magnetic. When their spins are random, the material isn’t. An applied current can align or randomize the spins, allowing for spin-based switches.

Intel has announced that is developing a system-on-chip for embedded applications based around its Atom processor core. However, it appears the SoC will be of a fixed design with a PCI Express bus interface to which system-level customers can attach their own or third-party chips. Similarly it appears that Intel will manufacture the system-chip internally rather than allowing a foundry to make the chip, or add its customers' IP to the design. Doug Davis, corporate vice president and general manager of Intel's embedded and communications group, disclosed details of the "Tunnel Creek" SoC during his keynote speech on Wednesday (April 14) at the Intel Developer Forum, in Beijing China.

How's this for a wedge issue on a slow news week? When Xilinx announced earlier this year that it was changing one of its foundry suppliers from UMC to TSMC for the 28-nm node, it seemed like a blow to differentiation—at least from a process technology standpoint—between Xilinx and Altera, which has been using TSMC for years. But while Xilinx chose to go with TSMC's high-performance/low power process, Altera said this week it is going with TSMC's high-performance process. Altera maintains that customers in the high end communications equipment market are much more concerned about performance than power. Luanne Schirrmeister, senior director of product marketing at Altera, put it this way: "In communications infrastructure, nothing is battery powered. Everything is plugged into a wall."

Avnet Electronics Marketing and Xilinx Inc. said they have concluded their five-month, 37-city global X-fest technical seminar series. According to the companies, the free one-day training sessions offered practical, how-to system level design instruction featuring the Spartan-6 and Virtex-6 FPGA families from Xilinx, as well as key enabling technologies from suppliers including Cypress Semiconductor, Intel, Maxim Integrated Products, National Semiconductor, NXP, Texas Instruments and Tyco Electronics. Replays of the events are available online.

I remember when, a decade ago, Kevin Warwick, a professor at the University of Reading, in the U.K., implanted a radio chip in his own arm. The feat caused quite a stir. The implant allowed him to operate doors, lights, and computers without touching anything. On a second version of the project he could even control an electric wheelchair and produce artificial sensations in his brain using the implanted chip. Warwick had become, in his own words, a cyborg. The idea of a cyborg -- a human-machine hybrid -- is common in science fiction and although the term dates back to the 1960s it still generates a lot of curiosity. I often hear people asking, When will we become cyborgs? When will humans and machines merge? Although some researchers might have specific time frames in mind, I think a better answer is: It's already happening. When we look back at the history of technology, we tend to see distinct periods -- before the PC and after the PC, before the Internet and after the Internet, and so forth -- but in reality most technological advances unfold slowly and gradually. That's particularly true with the technologies that are allowing us to modify and enhance our bodies.

The FPGAs referenced in these articles have complex dedicated I/O circuitries that are primarily designed to support external memory interfaces. The ALTMEMPHY megafunction is designed to support the most common memory standards, such as the DDR and DDR 2 SDRAM and QDR II+/QDR II SRAM (in a burst length of 4) interfaces. The ALTMEMPHY megafunction should be used whenever possible as it is beneficial to use the IP and timing closure methodologies used with these FPGAs, which enables users not to have to create this function manually as compared with using the ALTDLL and ALTDQ_DQS solution. However, the ALTMEMPHY megafunction does not support other external memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2) or customized DDR and DDR 2 SDRAM external memory standards. For these scenarios, use the ALTDLL and ALTDQ_DQS megafunctions to access the FPGA architecture and build a custom external memory interface.

While the new multicore system on chip (SoC) signal-processing architecture announced by Texas Instruments this week at Mobile World Congress hits all the right notes with respect to what's needed in next-generation basestation designs, it rings a bit hollow given how sketchy the architectural details remain when contrasted with more 'real' announcements from the likes of Freescale. For sure, the requirements of next-generation basestations will push all architectures to their limits and beyond. Balancing lower power and lower cost with increasingly parallel, math-intensive processing to meet multiuser demands for high-data-rate data in 3GPP Long Term Evolution (LTE) Release 8 all-IP networks is not going to be easy, especially with the introduction of MIMO, beam forming, OFDMA and many other enhancements engineered to maximize spectral efficiency.

The race to create tiny wireless sensors that could monitor anything from pressure in the eyes and brain to the stability of bridges appears to be heating up. Earlier this month, IEEE Spectrum reported on two approaches to creating an almost-indefinitely-running sensor using piezoelectric systems to convert tiny vibrations into power. Now, another team from the University of Michigan has created an alternative approach that uses solar power to keep the sensor running autonomously for many years.

Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them. "There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec. On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.

A little more than a week after long-simmering programmable logic startup Tabula Inc. emerged from stealth mode, Tier Logic Inc. stepped into the light Wednesday (March 10), offering the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die. Like Tabula, Tier Logic's technology depends on a three-dimensional structure. But while Tabula uses rapid reconfiguration to, in the words of that firm's executives, treat time as the third dimension, Tier Logic's approach separates user circuits and configuration circuits into 3-D stacked layers, creating what the company calls the world's first monolithic 3-D FPGA.

This API provides users with a standard FPGA communication interface from C++ code. It is intended to encourage more widespread adoption of FPGAs and reconfigurable computing platforms—particularly among Windows application developers

When considering the resolution required for an A/D converter (ADC) integrated in a microcontroller (MCU), embedded systems designers must balance cost and performance. Higher ADC resolution implies higher-cost MCUs, but in some cases you can use other features in the MCU to enhance the ADC performance via software. That approach lets you achieve higher resolution using an inexpensive integrated ADC. Here's how to use of oversampling to achieve extra bits of resolution for an ADC integrated in an MCU.

You just built a breadboard of your expert design. You did all the simulations needed before going to layout, and reviewed the manufacturer's suggested techniques for a good thermal design for the particular package chosen. You even did your due diligence in going through the initial thermal analysis equations on paper to be sure not to exceed IC junction temperatures with a comfortable margin. But wait, you turn on the power and the IC is pretty hot to the touch. You are uncomfortable with this (not to mention the concern of your thermal experts and reliability people). Now what do you do?

Ted Marena of Lattice Semiconductor Corp., points out that designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function components on their printed circuit board. In addition to these digital functions, FPGAs and CPLDs can also implement common analog functions using an LVDS input, a simple resistor capacitor (RC) circuit and some FPGA or CPLD digital logic elements to create an analog to digital converter (ADC).

Experimental microbial fuel cells could turn bacteria into batteries that generate electricity from biomass. The key to this technology is the ability of bacteria to transfer electrons to their surroundings—for example, to the anode of a microbial fuel cell. But if the organisms have to be in direct contact with the anode, such devices would have to have extremely large surface areas. Researchers from Aarhus University, in Denmark, report today in the journal Nature that bacteria appear to conduct electricity while separated by several millimeters, at least a thousand times as far apart than previously demonstrated. The naturally occurring electric currents, if confirmed, would allow bacteria spaced at least 12 millimeters apart to communicate electrically. The discovery might lead to new paths to treating infection and a better understanding of microbial ecosystems.

It’s 2020, and it’s sunny outside. In fact, it’s so bright in your kitchen that you have to squint to see your grapefruit. You flip on your e-reader and the most recent e-issue of IEEE Spectrum pops up on-screen, the colors and text sharp and brilliant in the sunlight. There’s e-mail to answer, but you want to make the early commuter bus, so you roll up your e-reader and stuff it in your jacket pocket.

French service robotics company Robosoft has introduced a robot called Kompaï designed to assist elderly and disabled people and others who need special care. The mobile robot talks, understands speech, and can navigate autonomously. It reminds people of meetings, keeps track of shopping lists, plays music, and works as a videoconference system for users to talk with their doctors, for example. The video below is pretty awesome. It shows a senior at Broca Hospital, in Paris, interacting with the robot after receiving only a few minutes of training. The man asks the robot about the time, date, and whether he has any appointments that day; Kompaï gives answers in a computerized voice.

Cypress Semiconductor Corp. has launched a programmable product for data communication over existing power lines. The Powerline Communication product leverages the programmable analog and digital resources of Cypress's PSoC programmable system-on-a-chip architecture. It integrates multiple functions beyond communication, such as power measurement, system management and LCD drive. In addition to its flexibility and integration, the product offers greater than 97% packet success rates without retries and 100% success rates with retries built into the solution's coding, according to Cypress. It also offers the flexibility to communicate over high-voltage and low-voltage power lines for lighting and industrial control, home automation, automatic meter reading and smart energy management applications.

FPGAs referenced in this article have complex dedicated I/O circuitries that are primarily designed to support EMIF. The ALTMEMPHY megafunction is designed to support the most common memory standards, such as the DDR , DDR2 SDRAM, and QDR II+/QDR II SRAM (in a burst length of 4) interfaces. Other external memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2), or customized DDR and DDR 2 SDRAM external memory standards are not supported. Instead, the ALTDLL and ALTDQ_DQS megafunctions are used to access the FPGA architecture and build a custom EMIF.