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In addition to voice connectivity, digital cellular wireless networks such as GSM and its enhancement, GSM-EDGE, can now provide increased data speeds up to a (theoretical) limit of 384ﾠKbps. Third generation mobile networks, such as CDMA2000 and WCDMA or UMTS (Universal Mobile Telecommunications Standards) and TD-SCDMA (China only) are currently being deployed worldwide. These systems offer services such as video streaming, Internet browsing and, by using a technique called High Speed Packet Access (HSPA), they can in theory deliver downlink speeds up to 14,4 Mbps.

Events such as natural disasters, military actions, and public safety threats have led to an increased need for robust robots — especially ones that can travel across complex terrain in any dimension. The ability to scale vertical building surfaces or other structures offers unique capabilities in military applications such as urban reconnaissance, sensor deployment, and setting up urban network nodes. SRI's novel clamping technology, called compliant electroadhesion, has enabled the first application of this technology to wall-climbing robots that can help with these situations.  As the name implies, electroadhesion is an electrically controllable adhesion technology. It involves inducing electrostatic charges on a wall substrate using a power supply connected to compliant pads situated on the moving robot. SRI has demonstrated robust clamping to common building materials including glass, wood, metal, concrete, etc. with clamping pressures in the range of 0.5 to 1.5 N per square cm of clamp (0.8 to 2.3 pounds per square inch). The technology works on conductive and non-conductive substrates, smooth or rough materials, and through dust and debris. Unlike conventional adhesives or dry adhesives, the electroadhesion can be modulated or turned off for mobility or cleaning. The technology uses a very small amount of power (on the order of 20 microwatts/Newton weight held) and shows the ability to repeatably clamp to wall substrates that are heavily covered in dust or other debris.

Ever since graphene was first produced in a lab at the University of Manchester in 2004, researchers around the world have been fascinated with its potential in electronics applications. Graphene possessed all the benefits of carbon nanotubes (CNTs), namely its charged-carrier mobility, but it didn’t have any of the down sides, such as CNTs’ need for different processing techniques than silicon and the intrinsic difficulty of creating interconnects for CNTs. But all was not easy for applying graphene to electronics applications. One of the fundamental problems for graphene was its lack of a band gap, which left it with a very low on-off ratio measured at about 10 as compared to in the 100s for silicon. Now this fundamental hurdle has been overcome. Based on research led by Phaedon Avouris at IBM’s IBM T.J. Watson Research Center, Yorktown Heights, New York, IBM is reporting that they have created a significant band gap in graphene.

DSP core licensor Ceva Inc. is due to unveil a software-programmable multimedia video processor architecture at the Mobile World Congress in Barcelona next week. The multicore architecture, called MM3000, which comes complete with C compilers, power management provision and an RTOS/multithreading scheduler is intended to be able to process any and all video codecs up to the highest resolutions and frame rates currently available as well as future codecs for things like 3-D video.

French service robotics company Robosoft has introduced a robot called Kompaï designed to assist elderly and disabled people and others who need special care. The mobile robot talks, understands speech, and can navigate autonomously. It reminds people of meetings, keeps track of shopping lists, plays music, and works as a videoconference system for users to talk with their doctors, for example. The video below is pretty awesome. It shows a senior at Broca Hospital, in Paris, interacting with the robot after receiving only a few minutes of training. The man asks the robot about the time, date, and whether he has any appointments that day; Kompaï gives answers in a computerized voice.

Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them. "There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec. On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.

While the new multicore system on chip (SoC) signal-processing architecture announced by Texas Instruments this week at Mobile World Congress hits all the right notes with respect to what's needed in next-generation basestation designs, it rings a bit hollow given how sketchy the architectural details remain when contrasted with more 'real' announcements from the likes of Freescale. For sure, the requirements of next-generation basestations will push all architectures to their limits and beyond. Balancing lower power and lower cost with increasingly parallel, math-intensive processing to meet multiuser demands for high-data-rate data in 3GPP Long Term Evolution (LTE) Release 8 all-IP networks is not going to be easy, especially with the introduction of MIMO, beam forming, OFDMA and many other enhancements engineered to maximize spectral efficiency.

The FPGAs referenced in these articles have complex dedicated I/O circuitries that are primarily designed to support external memory interfaces. The ALTMEMPHY megafunction is designed to support the most common memory standards, such as the DDR and DDR 2 SDRAM and QDR II+/QDR II SRAM (in a burst length of 4) interfaces. The ALTMEMPHY megafunction should be used whenever possible as it is beneficial to use the IP and timing closure methodologies used with these FPGAs, which enables users not to have to create this function manually as compared with using the ALTDLL and ALTDQ_DQS solution. However, the ALTMEMPHY megafunction does not support other external memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2) or customized DDR and DDR 2 SDRAM external memory standards. For these scenarios, use the ALTDLL and ALTDQ_DQS megafunctions to access the FPGA architecture and build a custom external memory interface.