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Xilinx Inc. today introduced the architecture for a new Extensible Processing Platform they claim will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenges they face in designing today's embedded systems, which must meet ever-growing demands to perform highly complex functions. The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing - or any combination thereof - needed to meet their application-specific requirements, including lower cost and power.

National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing. The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.

Pico Computing has developed a signal processing library which is made up of a set of FPGA firmware components and related tools that speed the development and deployment of advanced video and network analytics for security, defense and aerospace applications.The library, which includes flexible components for signal analysis, feature detection, scale-space generation, correlation and filtering, has been validated and optimized for Pico Computing platforms based on the latest-generation Xilinx Virtex-5 and Virtex-6 FPGA devices.

CPU clock speeds have remained essentially constant over the last several years, resulting in the number of CPU's used in high-end systems rapidly increasing to keep up with the performance boosts expected by Moore's law. System size on the Top500 list has changed rapidly, and, in November 2009, the top ten systems averaged 134,893 cores, with five systems larger than 100,000 cores. This rapid increase of system size and the associated increase in the number of compute elements used in a single user job increase the urgency of dealing with system characteristics that impede application scalability.

A little over a mile from the Wolfram Research Europe Ltd. office, where I work, lies Blenheim Palace, which has a rather nice hedge maze. As I was walking around it on the weekend, I remembered a map solving example by Peter Overmann using new image processing features in an upcoming version of Mathematica. I was excited to apply the idea to this real-world example. Once back at my computer, I started by using Bing Maps to get the aerial photo (data created by Intermap, NAVTEQ, and Getmapping plc).

This book is intended for those who work in or provide components for industries that use digital signal processing (DSP). There is a wide variety of industries that utilize this technology. While the engineers who implement applications using DSP must be very familiar with the technology, there are many others who can benefit from a basic knowledge of its' fundamental principals, which is the goal of this book—to provide a basic tutorial on DSP.

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.

Model based Optical proximity correction is usually used to compensate for the pattern distortion during the microlithography process. Currently, almost all the lithography effects, such as the proximity effects from the limited NA, the 3D mask effects due to the shrinking critical dimension, the photo resist effects, and some other well known physical process, can all be well considered into modeling with the OPC algorithm. However, the micro-lithography is not the final step of the pattern transformation procedure from the mask to the wafer. The etch process is also a very important stage. It is well known that till now, the etch process still can't be well explained by physics theory. In this paper, we will demonstrate our study on the model based etch bias retarget for OPC.

Realistic sound rendering can directly impact the perceived realism of users of interactive media applications. An accurate acoustic response for a virtual environment is attuned according to the geometric representation of the environment. This response can convey important details about the environment, such as the location and motion of objects. The most common approach to sound rendering is a two-stage process: Sound propagation: the computation of impulse responses (IRs) that represent an acoustic space. Audio rendering: the generation of spatialized audio signal from the impulse responses and dry (anechoically recorded or synthetically generated) source signals.

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

Although signal processing is usually associated with digital signal processors, it is becoming increasingly evident that FPGAs are taking over as the platform of choice in the implementation of high-performance, high-precision signal processing. For many such applications, the choice generally boils down to using either a single FPGA, a FPGA with an associated DSP processor or a farm of DSP processors.

In then the past few years we have seen multiprocessing systems become more mainstream, in fact most modern personal computer CPUs now feature symmetric multiprocessing systems (SMP), where multiple instantiations of the same processor share the processing burden of the applications running on the PC. While SMPs are quite common today, we typically have not seen a shift towards multiprocessing in embedded computing. However, a new type of embedded design technique gives engineers the freedom to intelligently distribute processing functions across a digital subsystem. This article will look at an example of the distributed processing technique using Cypress Semiconductor's PSoC 3 and PSoC 5 architectures, which consist of a main CPU (in this case an 8051 or ARM Cortex M3), a DMA engine, and array of Universal Digital Blocks (UDB).

How's this for a wedge issue on a slow news week? When Xilinx announced earlier this year that it was changing one of its foundry suppliers from UMC to TSMC for the 28-nm node, it seemed like a blow to differentiation—at least from a process technology standpoint—between Xilinx and Altera, which has been using TSMC for years. But while Xilinx chose to go with TSMC's high-performance/low power process, Altera said this week it is going with TSMC's high-performance process. Altera maintains that customers in the high end communications equipment market are much more concerned about performance than power. Luanne Schirrmeister, senior director of product marketing at Altera, put it this way: "In communications infrastructure, nothing is battery powered. Everything is plugged into a wall."

Let’s face it. Most of the gear you use at work or play has multicore processors in it. Your laptop has them (the CPU itself has two cores, and the dedicated graphics processor has many more). That game console in the living room has still more, and even a high-end smartphone typically has a CPU and graphics core on a single chip. Out of sight but definitely not out of mind–particularly if they cease working–are the servers and high-throughput network routers, all which have numerous multicore processors in them. The multiple cores in these devices work in concert to provide quick responses to user queries or to manage the smooth flow of data throughout the office.

The World Wide Web Consortium has launched a new specification called "XProc," which provides a standard framework for composing XML processes.  It streamlines the automation, sequencing, and management of complex XML processes, the standards body said.  The "XML Pipeline Language" spec was developed to provide a framework for managing enterprise-level business processes.

An all-optical integrator, or lightwave capacitor, is a fundamental building block equivalent to those used in multi-functional electronic circuits. Associate Professor David Moss, a senior researcher within the Institute for Photonic and Optical Science (IPOS), leads an international team which has developed the optical integrator on a CMOS compatible silicon chip. The device, a photonic chip compatible with electronic technology (CMOS), will be a key enabler of next generation fully-integrated ultrafast optical data processing technologies for many applications including ultra-fast optical information-processing, optical memory, measurement, computing systems, and real-time differential equation computing units.

This article discusses the requirements, constraints and challenges in creating high-quality musical instruments using electronic components (both analog and digital) available today.

In mathematics, computer science, and related subjects, an 'algorithm' is an effective method for solving a problem expressed as a finite sequence of instructions. Algorithms are used for calculation, data processing, and many other fields. (In more advanced or abstract settings, the instructions do not necessarily constitute a finite sequence, or even a sequence; see, for example, "nondeterministic algorithm".) Each algorithm is a list of well-defined instructions for completing a task. Starting from an initial state, the instructions describe a computation that proceeds through a well-defined series of successive states, eventually terminating in a final ending state. The transition from one state to the next is not necessarily deterministic; some algorithms, known as randomized algorithms, incorporate randomness. [source = Bing Reference]