Electronic Everything!

STMicroelectronics has the STM8S Discovery kit for around US$7. For that little bit of money you get an 8 bit CPU with a detachable USB programming/debugging board and 32k of flash, 2k of RAM, and 1K of EEPROM. Downloadable tools include demo C compilers from a variety of third party vendors (limited to 16k, if I'm reading the literature correctly).

A transistor that emits light and is made from organic materials could lead to cheaper digital displays and fast-switching light sources on computer chips, according to the researchers who built it. Small displays made from diodes of the same type of materials (organic light-emitting diodes, or OLEDs) are already in commercial production, but the transistor design could improve on those and lead to applications where OLEDs can’t go. The new organic light-emitting transistor (OLET) is much more efficient than previous designs. It has an external quantum efficiency—a key measure of how much light comes out per charge carrier pumped in—of 5 percent. An OLED based on the same material has a quantum efficiency of only 2 percent. Previous OLET designs had an efficiency of only 0.6 percent.

A Product How-To on building a unified control environment using architectures such as TI’s Stellaris ARM Cortex-M3-based MCUs or Cortex-A8-based Sitara AM35x MPUs.

Synopsys, Inc., has unveiled the DesignWare Ethernet Quality-of-Service (QoS) Controller IP which implements the new IEEE specifications for audio video bridging (AVB) features. The DesignWare Ethernet IP solution supports the new IEEE 802.1AS and 802.1-Qav version D6.0 specifications. These specifications enable efficient networking of streaming audio video (AV) applications through IEEE 802.1 networks found in consumer electronics, automotive AV and professional sound system products. Synopsys' DesignWare Ethernet QoS Controller, which supports 10/100/1G data transfer speeds, allows designers to develop system-on-chips (SoCs) that deliver time-synchronized, low-latency audio and video over Ethernet networks with exceptional quality-of-service while retaining compatibility with legacy networks.

(Nanowerk News) While the laws of physics weren’t made to be broken, sometimes they need revision. A major current law has been rewritten thanks to the three-port transistor laser, developed by Milton Feng and Nick Holonyak Jr. at the University of Illinois.

Let’s face it. Most of the gear you use at work or play has multicore processors in it. Your laptop has them (the CPU itself has two cores, and the dedicated graphics processor has many more). That game console in the living room has still more, and even a high-end smartphone typically has a CPU and graphics core on a single chip. Out of sight but definitely not out of mind–particularly if they cease working–are the servers and high-throughput network routers, all which have numerous multicore processors in them. The multiple cores in these devices work in concert to provide quick responses to user queries or to manage the smooth flow of data throughout the office.

Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains. While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures. But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps. In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.

One of the biggest commercial applications of spintronics in computing to date has been the use of giant magnetoresistance (GMR), the material phenomenon that makes possible the huge storage capacity of today’s hard disk drives. In the awarding of the 2007 Nobel Prize in Physics, GMR was cited as the first big commercial application for nanotechnology. But extending the commercial application of spintronic-enabled systems beyond read heads for HDDs has proven to be a difficult task. One need only look at the seemingly endless travails of NVE Corporation, which in its financial results still shows it greatest revenue growth in contract research as opposed to product sales. While recent research from a team of researchers at Ohio State University and the University of Hamburg in Germany may not turn around the fortunes of spintronics in the short term, it does provide a way to better characterize the spin of electrons and thereby promises better ways of exploiting it for electronics applications. The researchers are reporting in Nature Nanotechnology that they have for the first time been able to create images of the spin direction of electrons.

FPGA devices create compelling business drivers generating a tidal wave of FPGA adoption for the implementation of system PCB designs. Obviously, the time to market advantages and capacity/performance characteristics of FPGA devices have delivered on the promise for a viable alternative to more capital resource intensive custom IC/ASIC solutions as well as a successful consolidation vehicle for standard "off the shelf" components in system design creation.

Xilinx Inc. today introduced the architecture for a new Extensible Processing Platform they claim will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenges they face in designing today's embedded systems, which must meet ever-growing demands to perform highly complex functions. The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing - or any combination thereof - needed to meet their application-specific requirements, including lower cost and power.

The design of a generator system requires many hours of detailed planning with the goal of creating an extremely reliable backup power source. Properly installed, the system will deliver the intended level of reliability. However, if incorrectly wired, the system can become a problem for both the owner and the manufacturer. While the generator installation can be handled by a range of people, from a trained technician to the typical homeowner, wiring mistakes can occur. Installation includes working with 120 VAC split phase, 240 V line voltage, along with low-voltage signals below 50 V. A small and easily made mistake, such as miswiring high voltage to low voltage, will destroy sensitive electronics quickly and may render the equipment inoperable. Thus, a resettable overcurrent and overvoltage solution capable of handling line voltage, electrostatic discharge (ESD), electrical fast transients (EFT), and current surge is required to protect low voltage interface circuits against this problem.

Samplify Systems Inc. (Santa Clara, Calif.) has announced an autofocus beamforming technology for ultrasound imaging. The technology uses a 32-channel ultrasound analog front-end receiver module in an ultra-small small-outline dual-in-line configuration based on the SAM1600 family of compressing ADCs.

Tiny semiconductor dots could lead to a new type of circuit based on magnetism rather than current flow. At least that’s the hope of researchers who’ve made the dots and are hoping to build them into a workable device. ”We want to make it into a so-called nonvolatile transistor,” says Kang Wang, head of the Device Research Laboratory at the University of California, Los Angeles. Such a ”spintronic” transistor would retain its logic state in the absence of current and require less power to switch a bit, reducing the electrical power required by a computer chip by as much as 99 percent. Wang’s research, supported in part by Intel, was published in March in the online version of Nature Materials. Where electronic transistors rely on the presence or absence of current to register the ones and zeros of digital logic, spintronic transistors depend on ”spin,” a quantum characteristic of the electron. Picture the electron as a rotating globe. When the north pole is pointing upward, that’s spin up; when pointing the other way, it’s spin down. When the spins of most electrons are aligned, the material is magnetic. When their spins are random, the material isn’t. An applied current can align or randomize the spins, allowing for spin-based switches.

Intel has announced that is developing a system-on-chip for embedded applications based around its Atom processor core. However, it appears the SoC will be of a fixed design with a PCI Express bus interface to which system-level customers can attach their own or third-party chips. Similarly it appears that Intel will manufacture the system-chip internally rather than allowing a foundry to make the chip, or add its customers' IP to the design. Doug Davis, corporate vice president and general manager of Intel's embedded and communications group, disclosed details of the "Tunnel Creek" SoC during his keynote speech on Wednesday (April 14) at the Intel Developer Forum, in Beijing China.

How's this for a wedge issue on a slow news week? When Xilinx announced earlier this year that it was changing one of its foundry suppliers from UMC to TSMC for the 28-nm node, it seemed like a blow to differentiation—at least from a process technology standpoint—between Xilinx and Altera, which has been using TSMC for years. But while Xilinx chose to go with TSMC's high-performance/low power process, Altera said this week it is going with TSMC's high-performance process. Altera maintains that customers in the high end communications equipment market are much more concerned about performance than power. Luanne Schirrmeister, senior director of product marketing at Altera, put it this way: "In communications infrastructure, nothing is battery powered. Everything is plugged into a wall."

Avnet Electronics Marketing and Xilinx Inc. said they have concluded their five-month, 37-city global X-fest technical seminar series. According to the companies, the free one-day training sessions offered practical, how-to system level design instruction featuring the Spartan-6 and Virtex-6 FPGA families from Xilinx, as well as key enabling technologies from suppliers including Cypress Semiconductor, Intel, Maxim Integrated Products, National Semiconductor, NXP, Texas Instruments and Tyco Electronics. Replays of the events are available online.

We've collected the most recent how-to and technical articles from Embedded.com on multithreading, multicores, multiprocessor-on-chip (MPoc), and multiprocessor system designs. We're constantly updating our lists of articles and industry links. Keep checking back to see what's new.

ON Semiconductor has expanded its multiplexer product line with devices that are designed to function at high input rates/clock frequencies. The NB6VQ572M, NB6LQ572, NB7L572, NB6L572M, NB7LQ572, NB6LQ572M, NB7VQ58M and NB7V58M mux/fanout devices are targeted at SONET, Gigabit Ethernet, Fiber Channel, backplane and other clock/data distribution applications. The NB6VQ572M and NB6LQ572M differential 4:1 clock/data input multiplexers with 1:2 current mode logic (CML) clock/data fanout buffers operate at up to 6 GHz/8 Gbps from a 1.8 V, 2.5 V or 3.3 V power supply. The new devices have a data dependent jitter of <10 ps and random clock jitter of less than 0.8 ps RMS.

Power and energy are key design considerations across a spectrum of computing solutions, from supercomputers and data centers to handheld phones and other mobile computers. A large body of work focuses on managing power and improving energy efficiency. While prior work is easily summarized in two words—"Avoid waste!"—the challenge is figuring out where and why waste happens and determining how to avoid it. In this article, I discuss how, at a general level, many inefficiencies, or waste, stem from the inherent way system architects address the complex trade-offs in the system-design process. I discuss common design practices that lead to power inefficiencies in typical systems and provide an intuitive categorization of high-level approaches to addressing them. The goal is to provide practitioners—whether in systems, packaging, algorithms, user interfaces, or databases—a set of tools, or "recipes," to systematically reason about and optimize power in their respective domains.

Understand an accelerator's particle-beam measurement and control challenge, and how engineers met it with leading-edge digitizing systems and associated techniques