Electronic Everything!

In what comes as a bit of a surprise, Fuji Soft Inc.’s new humanoid robot platform for hobbyists and researchers has been given the name PALRO (pal + robot).  Naturally we feel this name is a superb choice!  Sales to research institutions will begin on March 15th, 2010 with a general release following later in the year.  The robot combines Fuji Soft’s software prowess with an open architecture which will give developers plenty of room to experiment. PALRO stands 39.8cm (15″) tall and weighs 1.9kg (3.5 lbs), and here’s the good news: it costs 298,000 JPY ($3300 USD).  Considering PALRO has 20 DOF, a camera, 4 directional microphones, a speaker, LED arrays in its head and chest, 4 pressure sensors in each foot, 3-axis gyro sensor, an accelerometer, and an Intel Atom 1.6GHz CPU, it is priced very competitively.  A comparative robot kit like Vstone’s Robovie-PC for example, costs $1100 USD more and doesn’t have such a fancy exoskeleton.

In case you haven’t realized it, the new trend in computer chip technology is multi-core. This is where most of the speed improvements moving forward will come from on our computers. To take full advantage of this however it is necessary to design your applications using Parallel Programming practices, also known as "parallelism". In today’s episode, we will meet with Stephen Toub, who will share with us some of the overarching concepts associated with parallelism, and some of the ways we are trying to empower developers to develop applications to take advantage of it.

Icosatetraped does, in fact, mean “twenty-four legged.” I’m not sure how to inject “soft” into that word (icostatetrasquishaped?), but this robot does have 24 soft legs. Or rather, 8 legs are soft (and moving) at any one time, while the other 16 are pressurized to carry the weight of the bot. It can move at about 1 meter per minute, which isn’t especially fast, but who cares, look at all of those little legs go! Made from plastic medical tubing, particle board, a bunch of solenoids, a Mac Mini, and some 24 volt rotary vane compressors salvaged from Gulf War nerve gas detecting equipment, this is about as DIY as it gets, and it’s awesome.

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.

In then the past few years we have seen multiprocessing systems become more mainstream, in fact most modern personal computer CPUs now feature symmetric multiprocessing systems (SMP), where multiple instantiations of the same processor share the processing burden of the applications running on the PC. While SMPs are quite common today, we typically have not seen a shift towards multiprocessing in embedded computing. However, a new type of embedded design technique gives engineers the freedom to intelligently distribute processing functions across a digital subsystem. This article will look at an example of the distributed processing technique using Cypress Semiconductor's PSoC 3 and PSoC 5 architectures, which consist of a main CPU (in this case an 8051 or ARM Cortex M3), a DMA engine, and array of Universal Digital Blocks (UDB).

The first part of this white paper explores the basic concepts behind HDMI, the markets it serves and its leadership role in multimedia interfaces. This is followed by a tutorial on the new capabilities of HDMI 1.4 and their role in providing a richer, more straightforward user experience. Next, we'll explore a series of user case scenarios that illustrate how the HEAC feature can simplify cabling requirements between digital home multimedia devices. The last portion of this paper discusses the architectural considerations and technical details involved with incorporating the Ethernet and Sony/Philips Digital Interconnect Format (S/PDIF) standards into the HDMI system-on-chips (SoCs) to support the HEAC feature.

The IEEE has launched a new Web site that consolidates information about smart electric grids from it various societies. The portal is one of many activities from an IEEE smart grid initiative coordinating the organization's work on the transition to digital, networked power systems and services. The smart grid is "so interdisciplinary," said Wanda Reder, chair of the IEEE Smart Grid Task Force and former president of the IEEE Power & Energy Society. "We have the gamut covered in technical interests, but we needed a way to facilitate communications between our many entities to link information on all the conferences, papers and standards we have in this area," she added.

The consumer handheld market is growing by leaps and bounds. With more processing power and increased support for more applications, portable products are cross-pollinating with traditional computing systems even as the product life cycle has decreased considerably in this market segment. As a result, especially in this era of economic slowdown, it is imperative that new products meet the time-to-market window to gain maximum acceptance. A decrease in product life cycles requires a reduced development cycle and an increased emphasis on reusability and reprogrammability. The emerging handheld market is also seeing interesting trends in which each individual device in a family has lower volumes but there is more customization across the series of devices, effectively upping the total unit volumes. The key challenge then becomes how to develop a system that is widely reusable and also customizable. These requirements have led designers increasingly to turn to the FPGA for handheld-product development. The FPGA has become more powerful and feature-rich, while gate counts, area and frequency have increased. FPGA development and turnaround cycles are considerably shorter than those of custom ASICs, and the added advantage of reprogrammability can make the FPGA a more compelling solution for handheld embedded systems.

The first textbook of its kind, Programming Massively Parallel Processors: A Hands-on Approach launches today, authored by Dr. David B. Kirk, NVIDIA Fellow and former chief scientist, and Dr. Wen-mei Hwu, who serves at the University of Illinois at Urbana-Champaign as Chair of Electrical and Computer Engineering in the Coordinated Science Laboratory, co-director of the Universal Parallel Computing Research Center and principal investigator of the CUDA Center of Excellence. The textbook, which is 256 pages, is the first aimed at teaching advanced students and professionals the basic concepts of parallel programming and GPU architectures. Published by Morgan Kaufmann, it explores various techniques for constructing parallel programs and reviews numerous case studies. With conventional CPU-based computing no longer scaling in performance and the world’s computational challenges increasing in complexity, the need for massively parallel processing has never been greater. GPUs have hundreds of cores capable of delivering transformative performance increases across a wide range of computational challenges. The rise of these multi-core architectures has raised the need to teach advanced programmers a new and essential skill: how to program massively parallel processors.

PC-compatible industrial computers are increasing in computing power at a rapid rate due to the availability of multi-core microprocessor chips, and Microsoft Windows has become the de-facto software platform for implementing human-machine interfaces (HMIs). PCs are also becoming more reliable. With these trends, the practice of building robotic systems as complex multi-architecture, multi-platform systems is being challenged. It is now becoming possible to integrate all the functions of machine control and HMI into a single platform, without sacrificing performance and reliability of processing. Through new developments in software, we are seeing industrial systems evolving to better integrate Windows with real-time functionality such as machine vision and motion control. Software support to simplify motion control algorithm implementation already exists for the Intel processor architecture.

Apple just announced the launch of the iPad, Apple's rumored tablet computer. Judging from what we have seen so far, the iPad is basically a very large iPod touch with a modified interface. According to Steve Jobs, the device will be far better than an iPhone or netbook for browsing the web. The iPad will also feature most of the standard apps we have become used to on the iPhone platform, including maps, contacts and a calendar.

The MAX13171E along with the MAX13173E/ MAX13175E, form a complete pin-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that support the V.28 (RS-232), V.10/V.11 (RS-449/V.36, RS-530, RS-530A, X.21), and V.35 protocols. The MAX13171E transceivers carry the high-speed clock and data signals, while the MAX13173E transceivers carry the control signals. The MAX13171E can be terminated by the MAX13175E pin-selectable resistor termination network. The MAX13175E contains six pin-selectable, multiprotocol cable termination networks.

Mahru-Z is the robotic maid that can make breakfast!. Given certain voice commands the robot can perform functions such as working a microwave, delivering toast, and other tasks such as washing clothes. The robots can see with stereoscopic vision and can identify what objects are and even decide what jobs needs to be done with the objects. In the video, one robot appears to be tethered and the other is not making me wonder if they are really self contained. Also, one is wearing a dress and the other not, so are they both maids or is one a butler? Shouldn't they just call them robotic servants or is that redundant? Regardless, although not apparently sentient, these do appear to be advanced robots. I only wonder if they washed their hands before and after handling the food?

Kota Nezu of ZNUG Design talks about his work developing the look of ZMP’s RoboCar, an educational platform for researchers working on autonomous vehicles.  The video is entirely Japanese, but you can see some cool CAD work and there’s some explanatory slides in this .PDF file.  Nezu-san also designed ZMP’s e-nuvo Humanoid, and Toyota’s personal transporter, the i-unit (seen in model form on his desk).  Part 2 follows after the break for those interested.

4 January 2010—Though flexible devices such as roll-up displays have been promised for several years, their commercialization has been stalled by a missing ingredient: a flexible form of flash memory. But researchers at the University of Tokyo have recently developed an organic, floating-gate nonvolatile memory that behaves like flash memory, which may solve that problem. While silicon-based flash memory is fine for the mass data storage found in cellphones, digital music players, and thumb drives, fabricating it requires high processing temperatures, thus ruling out its production on flexible substrates like plastic. Organic semiconductors, however, can be processed at temperatures well below the melting point of most plastics. What's more, "the cost of flash memory is too high to use in applications that require large arrays of memory," says Tsuyoshi Sekitani, an assistant professor in the University of Tokyo's department of electrical and electronic engineering and one of the researchers who developed the new memory. "But we can print our organic memory on flexible substrates and over large areas using inkjet printers. So costs will be low."