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A shielded transformer is a two-winding transformer, usually delta"star connected and serves the following purposes: Voltage transformation from the distribution voltage to the equipment's utilization voltage. Converting a 3-wire input power to a 4-wire output thereby deriving a separate stable neutral for the power supply wiring going to sensitive equipment. Keeping third and its multiple harmonics away from sensitive equipment by allowing their free circulation in the delta winding. Softening of high-frequency noise from the input side by the natural inductance

Rube Goldberg couldn’t have designed a more elegant confluence of convoluted causal relationships.  Start analyzing the perplexing paradox of the FPGA synthesis market and each link of the chain reveals a bizarre force vector that eventually doubles back onto itself into an unlikely equilibrium that miraculously has held stable for a full decade despite disruptive forces of epic proportions. For over a decade now, Synplify has navigated these waters and has continued to survive and thrive through the unlikeliest of conditions.  Now in the hands of EDA giant Synopsys, the Synplify family of FPGA synthesis tools continues to evolve - with a major upgrade this fall.  When you put a digital design into an FPGA, there are two technologies that determine whether your design fits or doesn’t fit, whether it meets your timing constraints or does not, whether the power consumption will be within your limits (or those of the FPGA), or whether it fails completely, leaving your project at the mercy of major mulligans.   Those two technologies are synthesis and place-and-route. 

Harmonic balance (hB) analysis is a method used to calculate the nonlinear, steady-state frequency response of electrical circuits. It is extremely well-suited for designs in which transient simulation methods prove acceptable, such as dispersive transmission lines in which circuit time constants are large compared to the period of the simulation frequency, as well as for circuits that have a large number of reactive components. In particular, harmonic balance analysis works extremely well for microwave circuits that are excited with sinusoidal signals, such as mixers and power amplifiers...

Robots mean many things to many people, and National Instruments offers intuitive and productive design tools for everything from designing autonomous vehicles to teaching robotics design principals. The NI LabVIEW graphical programming language makes it easy to program complex robotics applications by providing a high level of abstraction for sensor communication, obstacle avoidance, path planning, kinematics, steering, and more.

Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains. While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures. But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps. In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.

FPGA devices create compelling business drivers generating a tidal wave of FPGA adoption for the implementation of system PCB designs. Obviously, the time to market advantages and capacity/performance characteristics of FPGA devices have delivered on the promise for a viable alternative to more capital resource intensive custom IC/ASIC solutions as well as a successful consolidation vehicle for standard "off the shelf" components in system design creation.

Xilinx Inc. today introduced the architecture for a new Extensible Processing Platform they claim will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenges they face in designing today's embedded systems, which must meet ever-growing demands to perform highly complex functions. The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing - or any combination thereof - needed to meet their application-specific requirements, including lower cost and power.

When Pantelis Georgiou and his fellow biomedical engineers at Imperial College London decided to design an intelligent insulin pump for diabetes patients, they started at the source. "We asked ourselves, what does a pancreas do to control blood glucose?" Georgiou recalls. The answer is pretty well known: The organ relies primarily on two populations of cells—beta cells, to secrete insulin when blood glucose is high, and alpha cells, which release a hormone called glucagon when glucose levels are low. "We simulated them both in microchip form," Georgiou says. This biomimetic approach diverges from today's dominant method of delivering only insulin using a relatively simple control system.

In then the past few years we have seen multiprocessing systems become more mainstream, in fact most modern personal computer CPUs now feature symmetric multiprocessing systems (SMP), where multiple instantiations of the same processor share the processing burden of the applications running on the PC. While SMPs are quite common today, we typically have not seen a shift towards multiprocessing in embedded computing. However, a new type of embedded design technique gives engineers the freedom to intelligently distribute processing functions across a digital subsystem. This article will look at an example of the distributed processing technique using Cypress Semiconductor's PSoC 3 and PSoC 5 architectures, which consist of a main CPU (in this case an 8051 or ARM Cortex M3), a DMA engine, and array of Universal Digital Blocks (UDB).

While the new multicore system on chip (SoC) signal-processing architecture announced by Texas Instruments this week at Mobile World Congress hits all the right notes with respect to what's needed in next-generation basestation designs, it rings a bit hollow given how sketchy the architectural details remain when contrasted with more 'real' announcements from the likes of Freescale. For sure, the requirements of next-generation basestations will push all architectures to their limits and beyond. Balancing lower power and lower cost with increasingly parallel, math-intensive processing to meet multiuser demands for high-data-rate data in 3GPP Long Term Evolution (LTE) Release 8 all-IP networks is not going to be easy, especially with the introduction of MIMO, beam forming, OFDMA and many other enhancements engineered to maximize spectral efficiency.

March has seen two significant announcements from FPGA start-ups with innovative architectures: Tabula, with their time-domain-multiplexed architecture, and TierLogic, implementing their routing switches in a layer of thin-film transistors. Both approaches promise to significantly reduce the die size and cost of high-end FPGAs. But before these announcements broke, a relatively unnoticed paper at February's International Symposium on FPGAs described what may be the most radical technology of them all: FPGAs using electromechanical relays. No, this is not an early April Fool's joke, nor is it one of those "let's see if anyone will publish this one" academic exercises. The paper presented work by professors and students at the Stanford University departments of electrical engineering and computer science, and researchers at Altera Corp. The work was supported in part by DARPA funding.

Kota Nezu of ZNUG Design talks about his work developing the look of ZMP’s RoboCar, an educational platform for researchers working on autonomous vehicles.  The video is entirely Japanese, but you can see some cool CAD work and there’s some explanatory slides in this .PDF file.  Nezu-san also designed ZMP’s e-nuvo Humanoid, and Toyota’s personal transporter, the i-unit (seen in model form on his desk).  Part 2 follows after the break for those interested.

Analog Devices, Inc., has introduced a pair of Class-D audio amplifiers for smart phones, GPS units and other handheld electronics where premium sound quality offers a major competitive advantage. The SSM2375 and SSM2380 amplifiers provide audio system designers with the option of fixed or programmable gain settings combined with low noise and superior audio performance. The SSM2380 low-power, stereo Class-D amplifier is the first in its class to incorporate an I²C interface, which allows gain stages to be set from 1 dB to 24 dB (plus mute) in 47 distinct steps with no other external components required. The programmable interface also enables independent L/R channel shutdown, a variable low-EMI (electro-magnetic interference) emission control mode, and programmable ALC (automatic level control) functions for speaker protection. The SSM2380 achieves a 100-dB SNR (signal-to-noise ratio) and extends battery life by achieving 93 percent power efficiency at 5 V while running at 1.4 W into an 8-ohm speaker.

Intel has announced that is developing a system-on-chip for embedded applications based around its Atom processor core. However, it appears the SoC will be of a fixed design with a PCI Express bus interface to which system-level customers can attach their own or third-party chips. Similarly it appears that Intel will manufacture the system-chip internally rather than allowing a foundry to make the chip, or add its customers' IP to the design. Doug Davis, corporate vice president and general manager of Intel's embedded and communications group, disclosed details of the "Tunnel Creek" SoC during his keynote speech on Wednesday (April 14) at the Intel Developer Forum, in Beijing China.

The design of a generator system requires many hours of detailed planning with the goal of creating an extremely reliable backup power source. Properly installed, the system will deliver the intended level of reliability. However, if incorrectly wired, the system can become a problem for both the owner and the manufacturer. While the generator installation can be handled by a range of people, from a trained technician to the typical homeowner, wiring mistakes can occur. Installation includes working with 120 VAC split phase, 240 V line voltage, along with low-voltage signals below 50 V. A small and easily made mistake, such as miswiring high voltage to low voltage, will destroy sensitive electronics quickly and may render the equipment inoperable. Thus, a resettable overcurrent and overvoltage solution capable of handling line voltage, electrostatic discharge (ESD), electrical fast transients (EFT), and current surge is required to protect low voltage interface circuits against this problem.

When the Arduino Duemilanove microcontroller appeared in 2005, it featured a set of female pin headers exposing most of the pins of the ATmega168 for easy hacking and for connecting accessory boards known as 'Shields'. The purpose of a shield is to provide new plug-and-play functionality to the host microcontroller, such as circuit prototyping, motion control, sensor integration, network and radio communication, or gaming interfaces, without worrying too much about the hardware implementation details. Seven years after the birth of the original Arduino, new shields keep coming out and are being cataloged on http://shieldlist.org/, a testament to the versatility of the design. It is also simple to build a DIY shield when nothing out there will meet your needs or when you want to understand how the shield concept works from the ground up.