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Multisim 11 is the latest version of its circuit simulation software, with specialized editions for both hands-on learning and professional circuit design. The easy-to-use Multisim software delivers a graphical approach that abstracts the complexities of traditional circuit simulation, helping educators, students and engineers employ advanced circuit analysis technology. The academic edition of Multisim 11 incorporates specialized teaching features and is complemented by circuits textbooks and courseware. This integrated system helps educators engage students and reinforce circuit theory with an interactive, hands-on approach to investigating circuit behavior. Multisim 11 Professional helps engineers optimize circuit designs, minimize errors and reduce prototype iterations. When combined with the new NI Ultiboard 11 layout and routing software, Multisim provides engineers a cost-effective, end-to-end prototyping platform. Its integration with NI LabVIEW measurement software also helps engineers define custom analyses to improve design validation…

Given the maturity of MOSFETs, selecting one for your next design may seem deceptively simple. Engineers are familiar with the figures of merit on a MOSFET data sheet. Selecting a MOSFET requires the engineer to use their expertise in scrutinizing different specifications for individual applications. In an application such as a load switch in a server power supply, the switching aspects of a MOSFET matter little because the MOSFET is on almost 100% of the time. The on resistance (RDS(ON)) may be the key figure of merit in such an application. Still other applications, including switching power supplies, use MOSFETs as active switches, and cause the engineer to value other MOSFET performance parameters. Let us consider some applications and their prioritization of MOSFET specifications.

It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements.  Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.

At three separate industry events last week, engineers said they are gearing up to deliver in 2011 chips that can handle serial data streams running at 25 Gbits/second to drive next-generation 100 and 400 Gbit/second networks. But they say it's still a mystery how—or if—they can deliver follow-on components for the terabit networks today's Internet data centers are already demanding. The kinds of jobs required to run today's Web 2.0 services such as Google and Facebook can completely overwhelm current 10 Gbit/s Ethernet links in the warehouse-sized data centers those companies use. Such data centers could use hundreds of 100 Gbit/s Ethernet links today, although standards for such networks are still being completed.

With the introduction of the WEBENCH Online Design Environment in 1999, National Semiconductor made it possible for design engineers to create a reliable power supply circuit over the internet in minutes. The user specified the circuit performance and the WEBENCH Toolset delivered. Today, WEBENCH Designer creates and presents all of the possible power, lighting, or sensing circuits that meet a design requirement in seconds. This enables the user to make value based comparisons at a system and supply chain level before a design is committed. This expert analysis is not possible anywhere else.

When Pantelis Georgiou and his fellow biomedical engineers at Imperial College London decided to design an intelligent insulin pump for diabetes patients, they started at the source. "We asked ourselves, what does a pancreas do to control blood glucose?" Georgiou recalls. The answer is pretty well known: The organ relies primarily on two populations of cells—beta cells, to secrete insulin when blood glucose is high, and alpha cells, which release a hormone called glucagon when glucose levels are low. "We simulated them both in microchip form," Georgiou says. This biomimetic approach diverges from today's dominant method of delivering only insulin using a relatively simple control system.

By using a simple value process it is possible to speed up the analysis and help identify the best approach to take when developing a constant current regulation scheme for automotive interior LED lighting systems. Various approaches exist to address this particular design challenge that may result in a slowdown of the design process while engineering analysis can be performed to consider the advantages and disadvantages of the different options.

In traditional short-haul microwave transmission (that is, line-of-sight microwave transmissions operating in the 18 GHz and 23 GHz radio bands),RF design engineers typically are concerned with signal aspects such as fade margins, signal reflections, multipath signals, and so forth. Like an accountant seeking to balance a financial spreadsheet, an RF design engineer normally creates an RF budget table, expressed in decibels (dB), in order to establish a wireless design. Aspects like transmit power and antenna gain are registered in the assets (or plus) column, and free space attenuation, antenna alignment, and atmospheric losses are noted in the liabilities (or minus) column. The goal is to achieve a positive net signal strength adequate to support the wireless path(s) called for in the design.

The science behind gecko toes holds the answer to a dry adhesive that provides an ideal grip for robot feet. Stanford mechanical engineer Mark Cutkosky is using the new material, based on the structure of a gecko foot, to keep his robots climbing.

This book is intended for those who work in or provide components for industries that use digital signal processing (DSP). There is a wide variety of industries that utilize this technology. While the engineers who implement applications using DSP must be very familiar with the technology, there are many others who can benefit from a basic knowledge of its' fundamental principals, which is the goal of this book—to provide a basic tutorial on DSP.

In then the past few years we have seen multiprocessing systems become more mainstream, in fact most modern personal computer CPUs now feature symmetric multiprocessing systems (SMP), where multiple instantiations of the same processor share the processing burden of the applications running on the PC. While SMPs are quite common today, we typically have not seen a shift towards multiprocessing in embedded computing. However, a new type of embedded design technique gives engineers the freedom to intelligently distribute processing functions across a digital subsystem. This article will look at an example of the distributed processing technique using Cypress Semiconductor's PSoC 3 and PSoC 5 architectures, which consist of a main CPU (in this case an 8051 or ARM Cortex M3), a DMA engine, and array of Universal Digital Blocks (UDB).

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.

On Monday, National Instruments announced one such platform. It's called LabView Robotics. In addition to LabView, the popular data-acquisition application, the package includes a bunch of tools specific to robotics. It can import codes in various formats (C, C++, Matlab, VHDL), offers a library of drivers for a wide variety of sensors and actuators, and has modules for implementation of real-time and embedded hardware. NI says engineers could use the package to both design and run their robotic systems.