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With the consumer demand for richer content and its resultant , increasing high data bandwidth continuing to drive communications systems, coding for error control has become extraordinarily important. One way to improve the bit error rate (BER), while maintaining high data reliability, is to use an error correction technique like the Viterbi algorithm. Originally conceived by Andrew Viterbi as an error-correction scheme for noisy digital communication, the Viterbi algorithm provides an efficient method for forward error correction (FEC) that improves channel reliability. Today, it is used in many digital communications systems in applications as diverse as CDMA and GSM digital cellular, dial-up modems, satellite, deep-space communications and 802.11 wireless LANs. It is also commonly used in speech recognition, keyword spotting and computational linguistics.

At three separate industry events last week, engineers said they are gearing up to deliver in 2011 chips that can handle serial data streams running at 25 Gbits/second to drive next-generation 100 and 400 Gbit/second networks. But they say it's still a mystery how—or if—they can deliver follow-on components for the terabit networks today's Internet data centers are already demanding. The kinds of jobs required to run today's Web 2.0 services such as Google and Facebook can completely overwhelm current 10 Gbit/s Ethernet links in the warehouse-sized data centers those companies use. Such data centers could use hundreds of 100 Gbit/s Ethernet links today, although standards for such networks are still being completed.

4 January 2010—Though flexible devices such as roll-up displays have been promised for several years, their commercialization has been stalled by a missing ingredient: a flexible form of flash memory. But researchers at the University of Tokyo have recently developed an organic, floating-gate nonvolatile memory that behaves like flash memory, which may solve that problem. While silicon-based flash memory is fine for the mass data storage found in cellphones, digital music players, and thumb drives, fabricating it requires high processing temperatures, thus ruling out its production on flexible substrates like plastic. Organic semiconductors, however, can be processed at temperatures well below the melting point of most plastics. What's more, "the cost of flash memory is too high to use in applications that require large arrays of memory," says Tsuyoshi Sekitani, an assistant professor in the University of Tokyo's department of electrical and electronic engineering and one of the researchers who developed the new memory. "But we can print our organic memory on flexible substrates and over large areas using inkjet printers. So costs will be low."

Cypress Semiconductor Corp. has launched a programmable product for data communication over existing power lines. The Powerline Communication product leverages the programmable analog and digital resources of Cypress's PSoC programmable system-on-a-chip architecture. It integrates multiple functions beyond communication, such as power measurement, system management and LCD drive. In addition to its flexibility and integration, the product offers greater than 97% packet success rates without retries and 100% success rates with retries built into the solution's coding, according to Cypress. It also offers the flexibility to communicate over high-voltage and low-voltage power lines for lighting and industrial control, home automation, automatic meter reading and smart energy management applications.

Predicting trends is difficult even by the most connected industry experts, but one trend that's easy to spot is the widespread acceptance of multicore SoC. This is happening for a number of reasons. First, it's been years since the workstation first adopted the multicore processor architecture to solve such issues as increasing performance and power concerns. While the adoption rate in workstations is now saturated and is fully supported by General Purpose OSs (GPOS), the embedded world is just now looking at ways to adopt multicore architecture. Second, several SoC vendors have been providing multicore solutions including Cavium, Freescale, MIPS, and ARM; but up until now, these solutions have been limited to networking and used for performance enhancements rather than for low power. The rest of the embedded industry has had limited hardware options available as low-power design is a driving factor. While the ARM 11 MPCore was ahead of its time, the Cortex-A9 MPCore design is ready for primetime and is gaining acceptance in the embedded marketplace. As a result, SoC vendors have adopted the Cortex-A9 MPCore hardware as a basis for their next generation designs. Over a year ago, Texas Instruments pre-announced their next-generation OMAP designs in the OMAP 4 with a dual-core Cortex-A9 MPCore, scheduled for production in the second-half of 2010. ST Microsystems has pre-announced their next generation consumer devices which will be based on the Cortex A9 MPCore.

Xilinx Inc. today introduced the architecture for a new Extensible Processing Platform they claim will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenges they face in designing today's embedded systems, which must meet ever-growing demands to perform highly complex functions. The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing - or any combination thereof - needed to meet their application-specific requirements, including lower cost and power.