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Introduction to CRUD Functions in PHP - 0 views

  • Building a dynamic PHP site requires you to understand how CRUD (create, read, update, delete) functions work. There are a variety of ways to implement these functions include databases, and most commonly through mySQL.  With these functions you can add new entries to the database (registration), view existing entries (retrieve users or fields), update the entries to your table or delete users (who may unsubscribe or permanently delete their accounts.) For a user account based sites, these functions are essential for keeping your user and information database up to date.
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New DNA Assembly Line to Create Nanomaterials Efficiently - 0 views

  • "An industrial assembly line includes a factory, workers, and a conveyor system," said NYU Chemistry Professor Nadrian Seeman, the study's senior author. "We have emulated each of those features using DNA components." The assembly line relies on three DNA-based components. The first is DNA origami, a composition that uses a few hundred short DNA strands to direct a very long DNA strand to form structures to any desired shape. These shapes are approximately 100 x 100 nanometers in area, and about 2 nm thick (a nanometer is one billionth of a meter). DNA origami serves as the assembly line's framework and also houses its track. The second are three DNA machines, or cassettes, that serve as programmable cargo-donating devices. The cargo species the researchers used are gold nanoparticles, which measure 5 to 10 nanometers in diameter. Changing the cassette's control sequences allows the researchers to enable or prevent the donation of the cargoes to the growing construct. The third is a DNA "walker," which is analogous to the chassis of a car being assembled. It moves along the assembly line's track, stopping at the DNA machines to collect and carry the DNA "cargo." As the walker moves along the pathway prescribed by the origami tile track, it encounters sequentially the three DNA devices. These devices can be switched between an "on" state, allowing its cargo to be transferred to the walker, and an "off" state, in which no transfer occurs. In this way, the DNA product at the end of the assembly line may include cargo picked up from one, two, or three of the DNA machines. "A key feature of the assembly line is the programmability of the cargo-donating DNA machines, which allows the generation of eight different products," explained Seeman.
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F# in ASP.NET, mathematics and testing | .NET Zone - 0 views

  • Starting from Visual Studio 2010 F# is full member of .NET Framework languages family. It is functional language with syntax specific to functional languages but I think it is time for us also notice and study functional languages. In this posting I will show you some examples about cool things other people have done using F#.
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W3C Finishes XML Pipline Language Spec | Architects Zone - 0 views

  • The World Wide Web Consortium has launched a new specification called "XProc," which provides a standard framework for composing XML processes.  It streamlines the automation, sequencing, and management of complex XML processes, the standards body said.  The "XML Pipeline Language" spec was developed to provide a framework for managing enterprise-level business processes.
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Redefining electrical current law with the transistor laser - 0 views

  • (Nanowerk News) While the laws of physics weren’t made to be broken, sometimes they need revision. A major current law has been rewritten thanks to the three-port transistor laser, developed by Milton Feng and Nick Holonyak Jr. at the University of Illinois.
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The Blue Talkz...: Enough Dubs 2 - 0 views

  • This has to have a blog post. =) I've been listening to this album for the past couple of days more or less non-stop... and I love it. Very nice collection of "bass-driven sounds from all over the world". Totally recommended. Check it out! =)
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Asymmetric Processing Makes the Most of Multicore Processors « The Embedded Beat - 0 views

  • Let’s face it. Most of the gear you use at work or play has multicore processors in it. Your laptop has them (the CPU itself has two cores, and the dedicated graphics processor has many more). That game console in the living room has still more, and even a high-end smartphone typically has a CPU and graphics core on a single chip. Out of sight but definitely not out of mind–particularly if they cease working–are the servers and high-throughput network routers, all which have numerous multicore processors in them. The multiple cores in these devices work in concert to provide quick responses to user queries or to manage the smooth flow of data throughout the office.
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Project to Develop Biomimetic Proton Conductive Membranes with Nanometer Thickness - 0 views

  • The goal of the MultiPlat project is to develop biomimetic proton conductive membranes with nanometer thickness (nanomembranes) through convergence of the number of fields. The primary application of this multipurpose nanotechnological platform is the next generation of fuel cells where it will replace the prevailing evolutionary modifications of the state of the art solutions.
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Concurrency Visualizer High Speed Tour | LarryLarsen | Channel 9 - 0 views

  • This 75-second video provides a quick introduction to the Concurrency Visualizer, a new profiling tool available in Visual Studio 2010. The Concurrency Visualizer enables you to look under the hood of your parallel applications and quickly discover performance bottlenecks. If you’re hungry to learn more, visit http://blogs.msdn.com/visualizeparallel.
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InfoQ: A Pattern Language for Parallel Programming - 0 views

  • Ralph Johnson presents a pattern language that he and his colleagues are working on in an attempt to solve the hard issues of parallel programming through a set of design patterns: Structural Patterns, Computational Patterns, Parallel Algorithm Strategy Patterns, Implementation Strategy Patterns, and Concurrent Execution Patterns.
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Embedded.com - Timing Closure on FPGAs - 0 views

  • Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains. While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures. But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps. In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.
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IEEE Spectrum: CyberWalk: Giant Omni-Directional Treadmill To Explore Virtual Worlds - 0 views

  • It's a problem that has long annoyed virtual reality researchers: VR systems can create a good experience when users are observing or manipulating the virtual world (think Michael Douglas in "Disclosure") but walking is another story. Take a stroll in a virtual space and you might end up with your face against a real-world wall. The same problem is becoming apparent in teleoperated robots. Imagine you were teleoperating a humanoid robot by wearing a sensor suit that captures all your body movements. You want to make the robot walk across a room at the remote location -- but the room you're in is much smaller. Hmm. Researches have built a variety of contraptions to deal with the problem. Like a huge hamster ball for people, for example. Or a giant treadmill. The CyberWalk platform is a large-size 2D omni-directional platform that allows unconstrained locomotion, adjusting its speed and direction to keep the user always close to the center. With a side of 5 meters, it's the largest VR platform in the world.
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Announcing our new, free, open API | face.com - 0 views

  • Today face.com is proud to announce the opening of our platform APIs! After scanning billions of photos and tagging over 50 million users through Photo Tagger and Photo Finder, we’re moving ahead with our goal of making face recognition approachable and available to all. In this open alpha stage, we’re letting any developer tap into our face detection and face recognition tech through simple REST API calls. Whether you’re looking to build a cool photo tagging application, create personalized e-cards or campaigns, or any other sci-fi idea that comes to mind, we’re here to serve. A friend of the company, world-famous programmer, developer and founder of Technorati David Sifry got an early look at our API.  In David’s own words: “I’ve been impressed with Face.com’s API, and their plan for working closely with developers to build great applications that incorporate face detection and face recognition. Open platforms like this one will enable the creation of exciting new applications that we’ve never seen before at scale.”
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Dr Dobbs - F#: Putting the 'Fun' into 'Functional' - 0 views

  • You would be forgiven if you thought the "F" in F# -- which made its debut as part of Visual Studio 2010 -- stands for "functional." After all, F# (pronounced "F sharp") is a functional programming language for the .NET Framework that combines the succinct, expressive, and compositional style of functional programming with the runtime, libraries, interoperability, and object model of .NET. But Don Syme, inventor of F# and leader of the team that incubated the language, has a different, truncated, and entirely whimsical definition. "In the F# team," says Syme, a principal researcher at Microsoft Research Cambridge, "We say, 'F is for Fun.' F# enables users to write simple code to solve complex problems. Programming with F# really does make many programming tasks simpler, and our users have consistently reported that they've found using the language enjoyable." Indeed, F#, which has been developed in a partnership between Microsoft Research and the Microsoft Developer Division, is already popular with the .NET developer community. The language is widely known in the academic community and among thought leaders, and the list of admirers will only increase as Visual F#, the result of a partnership between Microsoft Research Cambridge and Microsoft's Developer Division, becomes a first-class language in Visual Studio 2010.
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IEEE Spectrum: Virginia Tech's Humanoid Robot CHARLI Walks Tall - 0 views

  • Dennis Hong, a professor of mechanical engineering and director of Virginia Tech's Robotics & Mechanisms Laboratory, or RoMeLa, has created robots with the most unusual shapes and sizes -- from strange multi-legged robots to amoeba-like robots with no legs at all. Now he's unveiling a new robot with a more conventional shape: a full-sized humanoid robot called CHARLI, or Cognitive Humanoid Autonomous Robot with Learning Intelligence. The robot is 5-foot tall (1.52 meter), untethered and autonomous, capable of walking and gesturing. But its biggest innovation is that it does not use rotational joints. Most humanoid robots -- Asimo, Hubo, Mahru -- use DC motors to rotate various joints (typically at the waist, hips, knees, and ankles). The approach makes sense and, in fact, today's humanoids can walk, run, and climb stairs. However, this approach doesn't correspond to how our own bodies work, with our muscles contracting and relaxing to rotate our various joints.
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IEEE Spectrum: Spintronics Gets Boost from First Images Taken of the Spin of Electrons - 0 views

  • One of the biggest commercial applications of spintronics in computing to date has been the use of giant magnetoresistance (GMR), the material phenomenon that makes possible the huge storage capacity of today’s hard disk drives. In the awarding of the 2007 Nobel Prize in Physics, GMR was cited as the first big commercial application for nanotechnology. But extending the commercial application of spintronic-enabled systems beyond read heads for HDDs has proven to be a difficult task. One need only look at the seemingly endless travails of NVE Corporation, which in its financial results still shows it greatest revenue growth in contract research as opposed to product sales. While recent research from a team of researchers at Ohio State University and the University of Hamburg in Germany may not turn around the fortunes of spintronics in the short term, it does provide a way to better characterize the spin of electrons and thereby promises better ways of exploiting it for electronics applications. The researchers are reporting in Nature Nanotechnology that they have for the first time been able to create images of the spin direction of electrons.
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Speech synthesis and voice recognition development tools | Audio DesignLine - 0 views

  • Tigal announced the VoiceGP family of products under its VeeaR brand of voice and speech recognition products. The product family consists of the VoiceGP module and two development kits with bundled development software. It combines all the hardware and software required for easy and cost effective development and implementation of speech synthesis and multi-language speaker independent and speaker dependent speech recognition capabilities to virtually any application, says the manufacturer. The VoiceGP Module is based on Sensory's RSC-4128 mixed signal processor. Its 42x72mm footprint and two 28-pin connectors with 2.54mm pin spacing make the module breadboard friendly and suitable for prototype boards.
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Algorithmic delay and synchronization in MPEG audio codecs | Audio DesignLine - 0 views

  • A variety of audio compression technologies are being used today, each having a distinct advantage over the other in terms of compression ratio, coding delay, coding complexity or legacy system compatibility. This makes subset of audio codecs suited for particular systems and makes working with multiple audio compression technologies indispensable. In designing time-critical systems like conferencing, broadcast transcoding systems or be it in designing any audio and video play-out system, the knowledge of the delay encountered while audio encoding or decoding becomes critical.
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Leveraging FPGA in PCB system designs | Industrial Control Designline - 0 views

  • FPGA devices create compelling business drivers generating a tidal wave of FPGA adoption for the implementation of system PCB designs. Obviously, the time to market advantages and capacity/performance characteristics of FPGA devices have delivered on the promise for a viable alternative to more capital resource intensive custom IC/ASIC solutions as well as a successful consolidation vehicle for standard "off the shelf" components in system design creation.
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TechOnline | ADMS Signals: Nets of User-defined Type in Standard SystemVerilog for Even... - 0 views

  • A common requirement in digital-dominated mixed-signal verification is the need for purely event-driven models that imitate Spice or AMS blocks at low fidelity but high speed. Resolved record types are commonly used for this modeling style in VHDL-based flows. Unfortunately, SystemVerilog defines only one resolved net type, the logic type. A second, non-standard net type, wreal, has been borrowed from Verilog-AMS and, with proprietary extensions, added to some implementations of SystemVerilog. wreal is a single real value with a small, fixed set of resolution functions. It solves only a subset of the problems commonly encountered in event-driven analog modeling. In contrast, the ADMS_signals approach is completely general and extensible while still conforming strictly to the IEEE SystemVerilog standard. The stored data type can be any type that is legal in SystemVerilog, including arrays and structs (nested to arbitrary depth) and even class instances (objects). The resolution function is a user-supplied SystemVerilog function. Different networks in the same design hierarchy may be given distinct stored type and resolution function.
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