Electronic Everything!

In case you haven’t realized it, the new trend in computer chip technology is multi-core. This is where most of the speed improvements moving forward will come from on our computers. To take full advantage of this however it is necessary to design your applications using Parallel Programming practices, also known as "parallelism". In today’s episode, we will meet with Stephen Toub, who will share with us some of the overarching concepts associated with parallelism, and some of the ways we are trying to empower developers to develop applications to take advantage of it.

Icosatetraped does, in fact, mean “twenty-four legged.” I’m not sure how to inject “soft” into that word (icostatetrasquishaped?), but this robot does have 24 soft legs. Or rather, 8 legs are soft (and moving) at any one time, while the other 16 are pressurized to carry the weight of the bot. It can move at about 1 meter per minute, which isn’t especially fast, but who cares, look at all of those little legs go! Made from plastic medical tubing, particle board, a bunch of solenoids, a Mac Mini, and some 24 volt rotary vane compressors salvaged from Gulf War nerve gas detecting equipment, this is about as DIY as it gets, and it’s awesome.

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.

In then the past few years we have seen multiprocessing systems become more mainstream, in fact most modern personal computer CPUs now feature symmetric multiprocessing systems (SMP), where multiple instantiations of the same processor share the processing burden of the applications running on the PC. While SMPs are quite common today, we typically have not seen a shift towards multiprocessing in embedded computing. However, a new type of embedded design technique gives engineers the freedom to intelligently distribute processing functions across a digital subsystem. This article will look at an example of the distributed processing technique using Cypress Semiconductor's PSoC 3 and PSoC 5 architectures, which consist of a main CPU (in this case an 8051 or ARM Cortex M3), a DMA engine, and array of Universal Digital Blocks (UDB).

Recent advances in the size and performance of FPGAs, coupled with advantages in time-to-market, field-reconfigurability and lower up-front costs, make FPGAs ideally suited to a wide range of commercial and defense applications [6]. In addition, FPGAs generality and reconfigurability provide important protections against the introduction of Trojan horses during semiconductor manufacturing process[8]. As a result, FPGA applications increasingly involve highly-sensitive intellectual property and trade-secrets, as well as cryptographic keys and algorithms [7].

One of the biggest commercial applications of spintronics in computing to date has been the use of giant magnetoresistance (GMR), the material phenomenon that makes possible the huge storage capacity of today’s hard disk drives. In the awarding of the 2007 Nobel Prize in Physics, GMR was cited as the first big commercial application for nanotechnology. But extending the commercial application of spintronic-enabled systems beyond read heads for HDDs has proven to be a difficult task. One need only look at the seemingly endless travails of NVE Corporation, which in its financial results still shows it greatest revenue growth in contract research as opposed to product sales. While recent research from a team of researchers at Ohio State University and the University of Hamburg in Germany may not turn around the fortunes of spintronics in the short term, it does provide a way to better characterize the spin of electrons and thereby promises better ways of exploiting it for electronics applications. The researchers are reporting in Nature Nanotechnology that they have for the first time been able to create images of the spin direction of electrons.

Predicting trends is difficult even by the most connected industry experts, but one trend that's easy to spot is the widespread acceptance of multicore SoC. This is happening for a number of reasons. First, it's been years since the workstation first adopted the multicore processor architecture to solve such issues as increasing performance and power concerns. While the adoption rate in workstations is now saturated and is fully supported by General Purpose OSs (GPOS), the embedded world is just now looking at ways to adopt multicore architecture. Second, several SoC vendors have been providing multicore solutions including Cavium, Freescale, MIPS, and ARM; but up until now, these solutions have been limited to networking and used for performance enhancements rather than for low power. The rest of the embedded industry has had limited hardware options available as low-power design is a driving factor. While the ARM 11 MPCore was ahead of its time, the Cortex-A9 MPCore design is ready for primetime and is gaining acceptance in the embedded marketplace. As a result, SoC vendors have adopted the Cortex-A9 MPCore hardware as a basis for their next generation designs. Over a year ago, Texas Instruments pre-announced their next-generation OMAP designs in the OMAP 4 with a dual-core Cortex-A9 MPCore, scheduled for production in the second-half of 2010. ST Microsystems has pre-announced their next generation consumer devices which will be based on the Cortex A9 MPCore.

A new chink has been found in the cryptographic armor that protects bank transactions, credit-card payments, and other secure Internet traffic. And although programmers have devised a patch for it, clever hackers might still be able to break through. The hack, presented in March at a computer security conference in Dresden, Germany, involves lowering the input voltage on a computer’s cryptography chip set and collecting the errors that leak out when the power-starved chips try and (sometimes) fail to encode messages. Crooks would then use those errors to reconstruct the secret key on which the encryption is based. More important, say the hack’s creators, the same attack could also be performed from afar on stressed systems, such as computer motherboards that run too hot or Web servers that run too fast.

NXP BV (Eindhoven, The Netherlands) has said it will demonstrate a microcontroller based on the ARM Cortex-M4 at the Embedded Systems Conference in San Jose, California. NXP was one of the first companies to license the Cortex-M4 processor core and a chip has been implemented using a low-leakage 90-nm process technology. This enables performance in excess of 150-MHz clock frequency, NXP said. NXP has added proprietary power-down techniques to reduce power consumption. The ESC Silicon Valley demo will show that a 7-channel audio graphic equalizer application processing 32-bit precision audio data requires only 12 MHz of CPU bandwidth using the Cortex-M4 DSP extensions, and 60 MIPs without. The core includes DSP extensions not usually found inside a microcontroller and NXP's implementation are aimed at a broad set of applications including motor control, digital power control and embedded audio.

Breadboarding a new circuit is a key skill and an important step in many projects—especially early on, when you need to move wires around and substitute components. But that very flexibility also makes it easy to knock wires out. Eventually, if your project is a keeper, you’re going to want something with a bit more permanence. Printed circuit boards (PCBs) solve all those shortcomings. But most people don’t even consider translating a one-off project into a PCB design. For one thing, PCB fabrication has traditionally been expensive, viable only in commercial quantities. (One alternative is to do it yourself with etches and silk screens, a messy and time-consuming process.) Also, there are technical constraints involved with PCB designs that are daunting to the casual hobbyist. But it turns out that nowadays you can produce a professional PCB very inexpensively.

March has seen two significant announcements from FPGA start-ups with innovative architectures: Tabula, with their time-domain-multiplexed architecture, and TierLogic, implementing their routing switches in a layer of thin-film transistors. Both approaches promise to significantly reduce the die size and cost of high-end FPGAs. But before these announcements broke, a relatively unnoticed paper at February's International Symposium on FPGAs described what may be the most radical technology of them all: FPGAs using electromechanical relays. No, this is not an early April Fool's joke, nor is it one of those "let's see if anyone will publish this one" academic exercises. The paper presented work by professors and students at the Stanford University departments of electrical engineering and computer science, and researchers at Altera Corp. The work was supported in part by DARPA funding.

Related to the strong demands for virtualization technology, network I/O virtualization has recently become a hot topic and is one of the key topics being discussed at the upcoming Multicore Expo @ ESC. In fact, analyst firm IDC, in a recent white paper titled "Optimizing I/O Virtualization: Preparing the Data Center for Next-Generation Applications", stated that "If I/O is not sufficient, then it could limit all the gains brought about by the virtualization process."

LED luminaires require precise power and heat management because LEDs convert most of the electrical energy they receive into heat rather than light. Without adequate thermal management, this heat can degrade the LED's life span and affect color output. Also, LEDs can fail short because they are silicon devices, so they may require fail-safe backup in the form of overcurrent protection. Resettable PPTC (polymeric-positive-temperature-coefficient) circuit-protection devices have demonstrated their effectiveness in a variety of LED-lighting applications. Like traditional fuses, they limit current after they exceed specified limits. However, unlike fuses, PPTC devices can reset after the fault clears and the power cycles.

25 March 2010—Nowadays, a phone that doesn’t know where it is or where it’s going can’t really call itself ”smart.” To orient themselves properly, smartphones require not just GPS capability but also an electronic compass, an accelerometer, and increasingly, digital gyroscopes. The point of a gyroscope is to sense any change in an object’s axis of rotation. Up until now, gyroscopes measured movement around the three axes with three sensors—one for pitch, one for yaw, and another for roll. At most, two of these sensors would be combined on a single die. The best you could do was, say, match up a 3- by 5- by 1-millimeter yaw sensor with a 4- by 5- by 1-mm sensor that would detect pitch and roll. But on 15 February, STMicroelectronics unveiled  a 4- by 4- by 1-mm gyroscope whose single sensing structure tracks all three angular motions. It’s a triumph of microelectromechanical systems (MEMS) engineering.

Linear and nonlinear device models are costly and time-consuming to develop. Most compact model parameters are extracted from linear, 50-ohm S-parameters and predicting behavior under extreme nonlinear conditions or non-50 ohm terminations is unreliable. This white paper entitled "X-parameters and Beyond, AWR's Support of PHD and Nonlinear Behavioral Models," provides details on rapidly-emerging nonlinear models and measurement systems and how Thye are employed in AWR's Microwave Office high-frequency design software.

ON Semiconductor has expanded its multiplexer product line with devices that are designed to function at high input rates/clock frequencies. The NB6VQ572M, NB6LQ572, NB7L572, NB6L572M, NB7LQ572, NB6LQ572M, NB7VQ58M and NB7V58M mux/fanout devices are targeted at SONET, Gigabit Ethernet, Fiber Channel, backplane and other clock/data distribution applications. The NB6VQ572M and NB6LQ572M differential 4:1 clock/data input multiplexers with 1:2 current mode logic (CML) clock/data fanout buffers operate at up to 6 GHz/8 Gbps from a 1.8 V, 2.5 V or 3.3 V power supply. The new devices have a data dependent jitter of <10 ps and random clock jitter of less than 0.8 ps RMS.

FPGA devices create compelling business drivers generating a tidal wave of FPGA adoption for the implementation of system PCB designs. Obviously, the time to market advantages and capacity/performance characteristics of FPGA devices have delivered on the promise for a viable alternative to more capital resource intensive custom IC/ASIC solutions as well as a successful consolidation vehicle for standard "off the shelf" components in system design creation.

Xilinx Inc. today introduced the architecture for a new Extensible Processing Platform they claim will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenges they face in designing today's embedded systems, which must meet ever-growing demands to perform highly complex functions. The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing - or any combination thereof - needed to meet their application-specific requirements, including lower cost and power.

The design of a generator system requires many hours of detailed planning with the goal of creating an extremely reliable backup power source. Properly installed, the system will deliver the intended level of reliability. However, if incorrectly wired, the system can become a problem for both the owner and the manufacturer. While the generator installation can be handled by a range of people, from a trained technician to the typical homeowner, wiring mistakes can occur. Installation includes working with 120 VAC split phase, 240 V line voltage, along with low-voltage signals below 50 V. A small and easily made mistake, such as miswiring high voltage to low voltage, will destroy sensitive electronics quickly and may render the equipment inoperable. Thus, a resettable overcurrent and overvoltage solution capable of handling line voltage, electrostatic discharge (ESD), electrical fast transients (EFT), and current surge is required to protect low voltage interface circuits against this problem.

Samplify Systems Inc. (Santa Clara, Calif.) has announced an autofocus beamforming technology for ultrasound imaging. The technology uses a 32-channel ultrasound analog front-end receiver module in an ultra-small small-outline dual-in-line configuration based on the SAM1600 family of compressing ADCs.