Electronic Everything!

Rube Goldberg couldn’t have designed a more elegant confluence of convoluted causal relationships.  Start analyzing the perplexing paradox of the FPGA synthesis market and each link of the chain reveals a bizarre force vector that eventually doubles back onto itself into an unlikely equilibrium that miraculously has held stable for a full decade despite disruptive forces of epic proportions. For over a decade now, Synplify has navigated these waters and has continued to survive and thrive through the unlikeliest of conditions.  Now in the hands of EDA giant Synopsys, the Synplify family of FPGA synthesis tools continues to evolve - with a major upgrade this fall.  When you put a digital design into an FPGA, there are two technologies that determine whether your design fits or doesn’t fit, whether it meets your timing constraints or does not, whether the power consumption will be within your limits (or those of the FPGA), or whether it fails completely, leaving your project at the mercy of major mulligans.   Those two technologies are synthesis and place-and-route. 

Ted Marena of Lattice Semiconductor Corp., points out that designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function components on their printed circuit board. In addition to these digital functions, FPGAs and CPLDs can also implement common analog functions using an LVDS input, a simple resistor capacitor (RC) circuit and some FPGA or CPLD digital logic elements to create an analog to digital converter (ADC).

RoweBots Research, Inc., a supplier of tiny embedded POSIX RTOS products, today announced the launch and release of UnisonTM Version 5 and the open-source version of Unison Version 4. These two ultra-tiny embedded-Linux and POSIX compatible RTOSs open Renesas Technology Corp.’s SH-2A Microcontroller (MCU) family to Linux and POSIX compatible development for the first time.

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.

The aptly-named StickyBot is a gecko-like robot that can climb smooth surfaces using its feet, which are covered in small, dry rubbery hairs (called setae on the gecko) which provide enough surface tension for dry adhesion. While the original StickyBot has 4 toes per foot, the team at Stanford has created the SB2 which has only 2 toes per foot while still retaining its climbing ability.

The marriage of high performance optics with microfluidics could prove the perfect match for making lab-on-a-chip technologies more practical. Microfluidics, the ability to manipulate tiny volumes of liquid, is at the heart of many lab-on-a-chip devices. Such platforms can automatically mix and filter chemicals, making them ideal for disease detection and environmental sensing. The performance of these devices, however, is typically inferior to larger scale laboratory equipment. While lab-on-a-chip systems can deliver and manipulate millions of liquid drops, there is not an equally scalable and efficient way to detect the activity, such as biological reactions, within the drops.

The goal of Long Term Evolution (LTE) is to achieve higher data rates through more efficient transmission, and thus improving the cellular phone user experience by enabling powerful new devices. The changes required in this technology present new challenges for base station vendors and their suppliers. Supporting 4G systems efficiently requires a number of innovations in DSP design; these innovations are moving the industry toward SoC architectures to support such systems. This paper will explore how TI's new architecture enables the key features in 4G systems.

Opus is Octasic's high-performing, ultra low-power, asynchronous DSP technology optimized for basestations, video processing and media gateway solutions. Asynchronous designs deliver similar computing performance to synchronous designs, but use less silicon and less power. No clock tree No state-elements Less sensitive to process and temperature variations

Hardware modifications and gadgets for ZX Spectrum and compatibles

Multisim 11 is the latest version of its circuit simulation software, with specialized editions for both hands-on learning and professional circuit design. The easy-to-use Multisim software delivers a graphical approach that abstracts the complexities of traditional circuit simulation, helping educators, students and engineers employ advanced circuit analysis technology. The academic edition of Multisim 11 incorporates specialized teaching features and is complemented by circuits textbooks and courseware. This integrated system helps educators engage students and reinforce circuit theory with an interactive, hands-on approach to investigating circuit behavior. Multisim 11 Professional helps engineers optimize circuit designs, minimize errors and reduce prototype iterations. When combined with the new NI Ultiboard 11 layout and routing software, Multisim provides engineers a cost-effective, end-to-end prototyping platform. Its integration with NI LabVIEW measurement software also helps engineers define custom analyses to improve design validation…

The potential for the QTC material to transition from an insulator to a conductor (i.e. change its electrical property) is influenced by how much deformation the material is experiencing as a result of the applied mechanical pressure. QTC can be used to produce low profile, low cost, pressure activated switches or sensors that display variable resistance with applied force and return to a quiescent state when the force is removed. The difference between a QTC switch and a QTC sensor is arguably only the speed and amount of physical input required to achieve the required switching point or resistance range.

Scientists have great expectations that nanotechnologies will bring them closer to the goal of creating computer systems that can simulate and emulate the brain's abilities for sensation, perception, action, interaction and cognition while rivaling its low power consumption and compact size. DARPA for instance, the U.S. military's research outfit known for projects that are pushing the envelope on what is technologically possible, has a program called SyNAPSE that is trying to develop electronic neuromorphic machine technology that scales to biological levels. Started in late 2008 and funded with $4.9 million, the goal of the initial phase of the SyNAPSE project is to "develop nanometer scale electronic synaptic components capable of adapting the connection strength between two neurons in a manner analogous to that seen in biological systems, as well as, simulate the utility of these synaptic components in core microcircuits that support the overall system architecture."

Not so long ago, artists routinely made their own paints using all sorts of odd ingredients: clay, linseed oil, ground-up insects—whatever worked. It was a crude and rather ad hoc process, but the results were used to create some of the greatest paintings in the world. Today I and other scientists are developing our own special paints. We’re not trying to compete with Vermeer or Gauguin, though. We hope to create masterpieces of a more technical nature: optoelectronic components that will make for better photovoltaic cells, imaging sensors, and optical communications equipment. And we’re not mixing and matching ingredients quite so haphazardly. Instead, we’re using our blossoming understanding of the world of nanomaterials to design the constituents of our paints at the molecular level.

While the new multicore system on chip (SoC) signal-processing architecture announced by Texas Instruments this week at Mobile World Congress hits all the right notes with respect to what's needed in next-generation basestation designs, it rings a bit hollow given how sketchy the architectural details remain when contrasted with more 'real' announcements from the likes of Freescale. For sure, the requirements of next-generation basestations will push all architectures to their limits and beyond. Balancing lower power and lower cost with increasingly parallel, math-intensive processing to meet multiuser demands for high-data-rate data in 3GPP Long Term Evolution (LTE) Release 8 all-IP networks is not going to be easy, especially with the introduction of MIMO, beam forming, OFDMA and many other enhancements engineered to maximize spectral efficiency.

The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these performances.In this article, we will detail how to assess rigorously power consumption, area, speed, code density and processing power for an embedded MCU. For each performance, we will describe how the parameters have to be selected to enable a fair comparison between processor cores.

Supporting the Wind River Systems VxWorks operating system on Intel architecture is valuable for customers who would like to preserve their application software and evaluate other architectures for comparison purposes or for architecture conversion. Products from Wind River Systems, particularly VxWorks, offer a great opportunity to address multiple architectures with the same real-time operating system (RTOS). Furthermore, the continuous development and migration of multicore platforms has increased the focus on migrating software to multicore and performance optimizations given a specified software workload and certain hardware resources.

DMA is used in almost every complex system or subsystems, but it's observed that teams either build the DMA controller from scratch for each project for specific application or take the existing DMAC available from elsewhere. This article discusses the architecture of DMAC that can be used with any kind of Bus, configuration (parallel, serial transfers), can be connected to any kind of ports, most importantly any kind of software assumptions can be implemented in the DMAC very easily.

The MiniZeni series from Sharp radiates high efficiency, deliver high color rendering index (CRI) values of up to 87 and boast a long service life whilst measuring only 15x12x1.6mm. The six new models of the MiniZeni series are characterised by four special features: they have compact outer dimensions and are extremely flat, economical and bright.

INTEL HELD AN EVENT in London last night to talk up its Core i3, i5 and i7 processors. To highlight the ceaseless march of technology and Chipzilla's own adherence to its beloved Moore's Law, the company was showcasing technology from the last 20 years as well as having a few demos about things we may expect to see in the future. Among these was this demonstration about the sorts of applications, such as advanced 3D rendering, that become feasible when a single processor can have 48 or more cores. µ

The ARM Cortex™-M4 processor is the latest embedded processor by ARM specifically developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors is designed to satisfy the emerging category of flexible solutions specifically targeting the motor control, automotive, power management, embedded audio and industrial automation markets. The Cortex-M4 processor features extended single-cycle multiply-accumulate (MAC) instructions, optimized SIMD arithmetic, saturating arithmetic instructions and an optional single precision Floating Point Unit (FPU). These features build upon the innovative technology that characterizes the ARM Cortex-M series processors…