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National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing. The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.

It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements.  Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.

In traditional short-haul microwave transmission (that is, line-of-sight microwave transmissions operating in the 18 GHz and 23 GHz radio bands),RF design engineers typically are concerned with signal aspects such as fade margins, signal reflections, multipath signals, and so forth. Like an accountant seeking to balance a financial spreadsheet, an RF design engineer normally creates an RF budget table, expressed in decibels (dB), in order to establish a wireless design. Aspects like transmit power and antenna gain are registered in the assets (or plus) column, and free space attenuation, antenna alignment, and atmospheric losses are noted in the liabilities (or minus) column. The goal is to achieve a positive net signal strength adequate to support the wireless path(s) called for in the design.

A shielded transformer is a two-winding transformer, usually delta"star connected and serves the following purposes: Voltage transformation from the distribution voltage to the equipment's utilization voltage. Converting a 3-wire input power to a 4-wire output thereby deriving a separate stable neutral for the power supply wiring going to sensitive equipment. Keeping third and its multiple harmonics away from sensitive equipment by allowing their free circulation in the delta winding. Softening of high-frequency noise from the input side by the natural inductance

In addition to voice connectivity, digital cellular wireless networks such as GSM and its enhancement, GSM-EDGE, can now provide increased data speeds up to a (theoretical) limit of 384ﾠKbps. Third generation mobile networks, such as CDMA2000 and WCDMA or UMTS (Universal Mobile Telecommunications Standards) and TD-SCDMA (China only) are currently being deployed worldwide. These systems offer services such as video streaming, Internet browsing and, by using a technique called High Speed Packet Access (HSPA), they can in theory deliver downlink speeds up to 14,4 Mbps.

High Level Synthesis Architectural Optimization Basics In part 1 of this article we introduced basic filter bank theory and used the Synplify DSP High Level Synthesis (HLS) tool to implement an example filter bank into three alternative architectures. In part 2 we dive deeper into these three architectures to better understand how these filters work. We will also examine the HLS optimizations we applied and the resulting benefits. Example Filter Bank Review Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample rate (red) has been chosen and the output sample rate is downsampled by 16 (green).

Imagine that a guest is about to depart from your house. She (or he) pauses to check her appearance in an antique-looking mirror mounted near the front door. Suddenly, the image of your guest undergoes a Matrix-like 'ripple' and is replaced with a strange face saying… …actually, we'll move on to consider what the face might say in a moment, but first let me introduce you to a few underlying concepts. Just a few days ago as I pen these words, I came across about a very cool website that describes a really cunning idea called a Magic Mirror (http://diymagicmirror.com).

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

Simple mathematical analysis shows that the best answer to address this problem is to  select a CR ratio QGD/QGS1 that is less than 1. Other factors to consider for preventing C dv/dt induced turn-on include low driver-sinking impedance (<1 Ώ), a FET design with intrinsically low RG, an externally-applied G-S capacitor and Q2 packages that minimize parasitics and voltage ringing.

Researchers at CMU and Intel are attempting to map and understand human brain activity well enough that individual words can be detected. Currently, giant MRI machines are being used but the future holds smaller devices that can be worn like a helmet according to Dean Pomerleau, senior researcher at Intel. The efficiency and productivity of word detection will be superior to existing technology that allows an operator to simply control a cursor. This technology will no doubt make its way into robotic telepresence applications including remote surgery and construction in dangerous environments such as the ocean and space.

Using a programmable device to expand the capabilities of an embedded system, designers can reduce power consumption at the same time By Rahul V. Shah and Vishesh Agrawal

Robots mean many things to many people, and National Instruments offers intuitive and productive design tools for everything from designing autonomous vehicles to teaching robotics design principals. The NI LabVIEW graphical programming language makes it easy to program complex robotics applications by providing a high level of abstraction for sensor communication, obstacle avoidance, path planning, kinematics, steering, and more.

Cypress Semiconductor Corp. has launched a programmable product for data communication over existing power lines. The Powerline Communication product leverages the programmable analog and digital resources of Cypress's PSoC programmable system-on-a-chip architecture. It integrates multiple functions beyond communication, such as power measurement, system management and LCD drive. In addition to its flexibility and integration, the product offers greater than 97% packet success rates without retries and 100% success rates with retries built into the solution's coding, according to Cypress. It also offers the flexibility to communicate over high-voltage and low-voltage power lines for lighting and industrial control, home automation, automatic meter reading and smart energy management applications.

Supporting the Wind River Systems VxWorks operating system on Intel architecture is valuable for customers who would like to preserve their application software and evaluate other architectures for comparison purposes or for architecture conversion. Products from Wind River Systems, particularly VxWorks, offer a great opportunity to address multiple architectures with the same real-time operating system (RTOS). Furthermore, the continuous development and migration of multicore platforms has increased the focus on migrating software to multicore and performance optimizations given a specified software workload and certain hardware resources.

A little more than a week after long-simmering programmable logic startup Tabula Inc. emerged from stealth mode, Tier Logic Inc. stepped into the light Wednesday (March 10), offering the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die. Like Tabula, Tier Logic's technology depends on a three-dimensional structure. But while Tabula uses rapid reconfiguration to, in the words of that firm's executives, treat time as the third dimension, Tier Logic's approach separates user circuits and configuration circuits into 3-D stacked layers, creating what the company calls the world's first monolithic 3-D FPGA.

The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these performances.In this article, we will detail how to assess rigorously power consumption, area, speed, code density and processing power for an embedded MCU. For each performance, we will describe how the parameters have to be selected to enable a fair comparison between processor cores.

Having the lowest system power allows customers to achieve their design objectives, whether it be for longer battery life, higher product performance or lower system cost. The Si100x/1x wireless MCU family features the industry’s lowest active mode current consumption, which saves power when the application is running. It also has the industry’s lowest current consumption sleep modes that save power when the device is sleeping, which is typically the majority of time in most battery powered applications.