Aasemoon'z Cluster

IBM's light-powered links overcome the greatest speed bump in supercomputing: interconnect bandwidth

Rube Goldberg couldn’t have designed a more elegant confluence of convoluted causal relationships.  Start analyzing the perplexing paradox of the FPGA synthesis market and each link of the chain reveals a bizarre force vector that eventually doubles back onto itself into an unlikely equilibrium that miraculously has held stable for a full decade despite disruptive forces of epic proportions. For over a decade now, Synplify has navigated these waters and has continued to survive and thrive through the unlikeliest of conditions.  Now in the hands of EDA giant Synopsys, the Synplify family of FPGA synthesis tools continues to evolve - with a major upgrade this fall.  When you put a digital design into an FPGA, there are two technologies that determine whether your design fits or doesn’t fit, whether it meets your timing constraints or does not, whether the power consumption will be within your limits (or those of the FPGA), or whether it fails completely, leaving your project at the mercy of major mulligans.   Those two technologies are synthesis and place-and-route. 

Embedded systems designers deserve better than the feature-lacking point-tools available today. Embedded designs should be more than a collection of microcontrollers and discrete components, pulled together by board design tools and software development environments that are not aware of each other presence, let alone integrated together. Programmable devices are not new. Embedded software is older than most of us! And a lot of embedded design is highly focused on specific interaction between the software and peripherals. So why do we still not have tools that bring all this together and make our lives easier and more productive?

After months of negotiation and delay, Warner Brothers and Metro-Goldwyn-Mayer are on the verge of an agreement that would allow the director Peter Jackson to begin shooting a two-part version of J. R. R. Tolkien’s “The Hobbit” early next year.

We had to cover monads eventually, and there are many great monad tutorials out there (see, for example, here: http://www.haskell.org/haskellwiki/Tutorials#Using_monads). In fact, there are web resources concerned solely with organizing the many monad tutorials available in the wild, and developing new monad tutorials seems to be a popular sport in the Haskell community.Today, Ralf Lämmel's lecture goes back to the roots, essentially revisiting Wadler's "The essence of functional programming"—the 1992 paper that discovered monads and popularized their use in functional programming. Ralf Lämmel's lecture and accompanying code distribution show Wadler's seminal insight: those original scenarios and observations still make sense today. Indeed, Simon Marlow (a Haskell/GHC high priest @ MSR Cambridge) recently noted: "it's still the best monad tutorial" (see http://twitter.com/simonmar/status/21397398061).

The MATLAB team at MathWorks tested performance scaling of the backslash ("\") matrix division operator to solve for x in the equation A*x = b. In their testing, matrix A occupies far more memory (290 GB) than is available in a single high-end desktop machine—typically a quad core processor with 4-8 GB of RAM, supplying approximately 20 Gigaflops. Therefore, they spread the calculation across machines. In order to solve linear systems of equations they need to be able to access all of the elements of the array even when the array is spread across multiple machines. This problem requires significant amounts of network communication, memory access, and CPU power. They scaled up to a cluster in EC2, giving them the ability to work with larger arrays and to perform calculations at up to 1.3 Teraflops, a 60X improvement. They were able to do this without making any changes to the application code. Here's a graph showing the near-linear scalability of an EC2 cluster across a range of matrix sizes with corresponding increases in cluster size for MATLAB's parallel backslash operator:

A research project will be conducted this week in Linz, Austria, to discover what the ideal interaction between people and humanoid robots ought to be in the future, Honda R&D and Ars Electronica Futurelab announced today. The research, the first of its kind in Europe, will involve members of the public directly interacting with ASIMO, Honda's humanoid robot.

If you need a quick reference guide for the UML notation, check one of the following, IMHO, gret UML cheat sheets (in no particular order):

In short, Joe argues, "Throughout, it became abundantly clear that TM, much like generics, was a systemic and platform-wide technology shift. It didn’t require type theory, but the road ahead sure wasn’t going to be easy." The whole blog post deals with how many implementation challenges platform-wide support for STM would be in .NET, including what options were considered. He does not mention Maurice Herlihy's SXM library approach, but refers to Tim Harris's work several times.

CPU clock speeds have remained essentially constant over the last several years, resulting in the number of CPU's used in high-end systems rapidly increasing to keep up with the performance boosts expected by Moore's law. System size on the Top500 list has changed rapidly, and, in November 2009, the top ten systems averaged 134,893 cores, with five systems larger than 100,000 cores. This rapid increase of system size and the associated increase in the number of compute elements used in a single user job increase the urgency of dealing with system characteristics that impede application scalability.

The conservation of Mayan wall paintings at the archaeological site of Calakmul (Mexico) will be one on the subjects touched upon by Piero Baglioni (based at the University of Florence) in his invited lecture at the 3rd European Chemistry Congress in Nürnberg in September. In a special issue of Chemistry-A European Journal, which contains papers by many of the speakers at this conference, he reports on the latest developments on the use of humble calcium and barium hydroxides nanoparticles as a versatile and highly efficient tool to combat the main degradation processes that affect wall paintings. La Antigua Ciudad Maya de Calakmul is located in the Campeche state (Mexico) and is one of the most important cities of the Classic Maya period (AD 250-800). The excavation of this site (set up in 1993) involves, under the supervision of the archaeologist Ramon Carrasco, archaeologists, architects, engineers, conservators and epigraphists, besides other specialists. Since 2004, the Center for Colloid and Surface Science (CSGI) at the University of Florence (CSGI), and currently directed by Piero Baglioni, has been an active partner, being involved in the study of the painting technique and in the development of nanotechnology for the consolidation and protection of the wall paintings and limestone.

Most multiprocessing systems can be classified as either symmetric multiprocessing (SMP) or asymmetric multiprocessing (AMP). AMP involves the use of interprocessor communication to combine the efforts of multiple processors, each with its own local operating system and hardware resources. Also, AMP involves less OS overhead for each individual processor and a more traditional execution environment for applications. AMP seems like distributed system. The number of peripherals that are supported in today's multicore processors is quickly increasing. Symmetric-multiprocessing (SMP) software is expected to be quickly available to support these peripherals. Basically any OS can be ported to a SMP platform, but the developers must take care of following issues for SMP OS. - Handling of task priority or implicit synchronization - Spinlocks and synchronization - Synchronization between tasks sharing memory - Synchronization between tasks and ISRs sharing memory - Synchronization between ISRs sharing memory

Usually developers consider Java as a programming language, but Java is a complete operating enviornment including some parts belong to OS. If you have experience of porting Java runtime to embedded system. You will find that RTOS is not a necessary requirement for porting Java.

When we first reported on the Willow Garage PR2 robot, it was just a prototype. Earlier this year, Willow Garage started their beta program, which gave eleven lucky organizations two year access to PR2 robots in exchange for furthering work on open source robotics software. Now we've received word from Willow Garage that the PR2 is officially for sale to anyone who wants it. This is not a toy or hobby robot, of course, so don't expect a small price tag. The full retail price is $400,000 per unit. However, if your organization can demonstrate a proven track record in developing open source software and making contributions to the robotics community, you can get a hefty $120,000 discount on your PR2. For more see our previous stories on Willow Garage and the PR2.

Erlang allows for massively scalable concurrency, often with millions of lightweight, thread-like components known as actors. Unfortunately, using Erlang requires rewriting all of your legacy code into a rather esoteric language. But there are other options, such as the little known CCR platform that was developed by .NET's robotics department. Actor based languages such as Erlang are able to achieve high degrees of parallelism by using the Actor model. Under this model the fundamental unit of concurrency is not a thread or fiber, but rather something much smaller. Known as a "process" in Erlang, each unit of concurrency has a base overhead of about 1200 bytes on a 32-bit system. By comparison, a thread on the Windows operating system defaults to 1 MB just for the stack, additional space is also needed for bookkeeping and thread local storage. Because they are so lightweight, an application can spawn literally millions of processes simultaneously.

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

Imagine that a guest is about to depart from your house. She (or he) pauses to check her appearance in an antique-looking mirror mounted near the front door. Suddenly, the image of your guest undergoes a Matrix-like 'ripple' and is replaced with a strange face saying… …actually, we'll move on to consider what the face might say in a moment, but first let me introduce you to a few underlying concepts. Just a few days ago as I pen these words, I came across about a very cool website that describes a really cunning idea called a Magic Mirror (http://diymagicmirror.com).

Researchers at CMU and Intel are attempting to map and understand human brain activity well enough that individual words can be detected. Currently, giant MRI machines are being used but the future holds smaller devices that can be worn like a helmet according to Dean Pomerleau, senior researcher at Intel. The efficiency and productivity of word detection will be superior to existing technology that allows an operator to simply control a cursor. This technology will no doubt make its way into robotic telepresence applications including remote surgery and construction in dangerous environments such as the ocean and space.

Xilinx Inc. today introduced the architecture for a new Extensible Processing Platform they claim will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenges they face in designing today's embedded systems, which must meet ever-growing demands to perform highly complex functions. The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing - or any combination thereof - needed to meet their application-specific requirements, including lower cost and power.