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The ARM Cortex™-M4 processor is the latest embedded processor by ARM specifically developed to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. The combination of high-efficiency signal processing functionality with the low-power, low cost and ease-of-use benefits of the Cortex-M family of processors is designed to satisfy the emerging category of flexible solutions specifically targeting the motor control, automotive, power management, embedded audio and industrial automation markets. The Cortex-M4 processor features extended single-cycle multiply-accumulate (MAC) instructions, optimized SIMD arithmetic, saturating arithmetic instructions and an optional single precision Floating Point Unit (FPU). These features build upon the innovative technology that characterizes the ARM Cortex-M series processors…

Pico Computing has developed a signal processing library which is made up of a set of FPGA firmware components and related tools that speed the development and deployment of advanced video and network analytics for security, defense and aerospace applications.The library, which includes flexible components for signal analysis, feature detection, scale-space generation, correlation and filtering, has been validated and optimized for Pico Computing platforms based on the latest-generation Xilinx Virtex-5 and Virtex-6 FPGA devices.

When I first heard about compressed sensing, I was skeptical. There were claims that it reduced the amount of data required to represent signals and images by huge factors and then restored the originals exactly. I knew from the Nyquist-Shannon sampling theorem that this is impossible. But after learning more about compressed sensing, I’ve come to realize that, under the right conditions, both the claims and the theorem are true. The Nyquist-Shannon sampling theorem states that to restore a signal exactly and uniquely, you need to have sampled with at least twice its frequency. Of course, this theorem is still valid; if you skip one byte in a signal or image of white noise, you can’t restore the original. But most interesting signals and images are not white noise. When represented in terms of appropriate basis functions, such as trig functions or wavelets, many signals have relatively few non-zero coefficients. In compressed (or compressive) sensing terminology, they are sparse.

In traditional short-haul microwave transmission (that is, line-of-sight microwave transmissions operating in the 18 GHz and 23 GHz radio bands),RF design engineers typically are concerned with signal aspects such as fade margins, signal reflections, multipath signals, and so forth. Like an accountant seeking to balance a financial spreadsheet, an RF design engineer normally creates an RF budget table, expressed in decibels (dB), in order to establish a wireless design. Aspects like transmit power and antenna gain are registered in the assets (or plus) column, and free space attenuation, antenna alignment, and atmospheric losses are noted in the liabilities (or minus) column. The goal is to achieve a positive net signal strength adequate to support the wireless path(s) called for in the design.

Earlier in this series, we touched on one problem that can arise when sampling an analog signal, namely the problem of aliasing. There are three other issues with signal sampling to which we now turn our attention: digitization effects, finite register length effects, and oversampling. So far, weve assumed that all of the signals were measuring are continuous analog values; i.e., our measurements are completely accurate. Even in the cases in which we have noise, the underlying assumption is that the measurement itself, for example the noisy sensor output voltage, is known precisely.

Although signal processing is usually associated with digital signal processors, it is becoming increasingly evident that FPGAs are taking over as the platform of choice in the implementation of high-performance, high-precision signal processing. For many such applications, the choice generally boils down to using either a single FPGA, a FPGA with an associated DSP processor or a farm of DSP processors.

Realistic sound rendering can directly impact the perceived realism of users of interactive media applications. An accurate acoustic response for a virtual environment is attuned according to the geometric representation of the environment. This response can convey important details about the environment, such as the location and motion of objects. The most common approach to sound rendering is a two-stage process: Sound propagation: the computation of impulse responses (IRs) that represent an acoustic space. Audio rendering: the generation of spatialized audio signal from the impulse responses and dry (anechoically recorded or synthetically generated) source signals.

This book is intended for those who work in or provide components for industries that use digital signal processing (DSP). There is a wide variety of industries that utilize this technology. While the engineers who implement applications using DSP must be very familiar with the technology, there are many others who can benefit from a basic knowledge of its' fundamental principals, which is the goal of this book—to provide a basic tutorial on DSP.

Length-match your traces to within 100 mils. Or is it 10 mils? Or should you go down to 1 mil? Should you include the lengths of the vias? How about the lengths of resistors? Understanding the origin of length-matching requirements, coupled with some rudimentary signal integrity analysis, can help answer these questions.   Determining length requirements requires an understanding of flight time, electrical length vs. physical length, loading and signal quality. Those elements are vital in determining what the length really needs to be, as well as in determining the allowable trade-offs to meet system timing goals.

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal processing has been implemented using fixed-point operations. This article describes how floating-point technology in FPGAs is not only practical today, but that the processing rates of one trillion floating-point operations per second (teraFLOPS) are feasible and can be implemented on a single FPGA die.

With the consumer demand for richer content and its resultant , increasing high data bandwidth continuing to drive communications systems, coding for error control has become extraordinarily important. One way to improve the bit error rate (BER), while maintaining high data reliability, is to use an error correction technique like the Viterbi algorithm. Originally conceived by Andrew Viterbi as an error-correction scheme for noisy digital communication, the Viterbi algorithm provides an efficient method for forward error correction (FEC) that improves channel reliability. Today, it is used in many digital communications systems in applications as diverse as CDMA and GSM digital cellular, dial-up modems, satellite, deep-space communications and 802.11 wireless LANs. It is also commonly used in speech recognition, keyword spotting and computational linguistics.

The MAX13171E along with the MAX13173E/ MAX13175E, form a complete pin-selectable data terminal equipment (DTE) or data communication equipment (DCE) interface port that support the V.28 (RS-232), V.10/V.11 (RS-449/V.36, RS-530, RS-530A, X.21), and V.35 protocols. The MAX13171E transceivers carry the high-speed clock and data signals, while the MAX13173E transceivers carry the control signals. The MAX13171E can be terminated by the MAX13175E pin-selectable resistor termination network. The MAX13175E contains six pin-selectable, multiprotocol cable termination networks.

Analog Devices, Inc., has introduced a pair of Class-D audio amplifiers for smart phones, GPS units and other handheld electronics where premium sound quality offers a major competitive advantage. The SSM2375 and SSM2380 amplifiers provide audio system designers with the option of fixed or programmable gain settings combined with low noise and superior audio performance. The SSM2380 low-power, stereo Class-D amplifier is the first in its class to incorporate an I²C interface, which allows gain stages to be set from 1 dB to 24 dB (plus mute) in 47 distinct steps with no other external components required. The programmable interface also enables independent L/R channel shutdown, a variable low-EMI (electro-magnetic interference) emission control mode, and programmable ALC (automatic level control) functions for speaker protection. The SSM2380 achieves a 100-dB SNR (signal-to-noise ratio) and extends battery life by achieving 93 percent power efficiency at 5 V while running at 1.4 W into an 8-ohm speaker.

A common requirement in digital-dominated mixed-signal verification is the need for purely event-driven models that imitate Spice or AMS blocks at low fidelity but high speed. Resolved record types are commonly used for this modeling style in VHDL-based flows. Unfortunately, SystemVerilog defines only one resolved net type, the logic type. A second, non-standard net type, wreal, has been borrowed from Verilog-AMS and, with proprietary extensions, added to some implementations of SystemVerilog. wreal is a single real value with a small, fixed set of resolution functions. It solves only a subset of the problems commonly encountered in event-driven analog modeling. In contrast, the ADMS_signals approach is completely general and extensible while still conforming strictly to the IEEE SystemVerilog standard. The stored data type can be any type that is legal in SystemVerilog, including arrays and structs (nested to arbitrary depth) and even class instances (objects). The resolution function is a user-supplied SystemVerilog function. Different networks in the same design hierarchy may be given distinct stored type and resolution function.

National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing. The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.

This article discusses the requirements, constraints and challenges in creating high-quality musical instruments using electronic components (both analog and digital) available today.

A new network design that avoids the need to convert optical signals into electrical ones could boost capacity while reducing power consumption.

This year's annual New York press briefing by the Edison Electric Institute, the organization representing investor-owned utilities, naturally was devoted to the smart grid, the hot topic of the day. Most notable, actually, was the absence of anything really new to report, which confirmed expectations that the smart grid will begin to prove itself next year at the earliest--or not. This was not the first EEI briefing devoted to smart grid prospects. Last year's briefing was devoted almost entirely to the smart meter avalanche, and a year or two before that much was made of Xcel Energy's SmartGridCity experiment in Boulder, Colorado. I reminded EEI president Thomas Kuhn of the Boulder briefing and pointed out that the experiment appears now to have been a failure. Kuhn did not dispute that and said it appears the problem in Boulder was that the target population was just too affluent: Despite the known green-mindedness of Boulderites, a major factor in Xcel's selecting the small city for its smart grid test run, it seems most of them do not care all that much about the modest monetary savings they stand to make from paying attention to electricity usage signals.

High Level Synthesis Architectural Optimization Basics In part 1 of this article we introduced basic filter bank theory and used the Synplify DSP High Level Synthesis (HLS) tool to implement an example filter bank into three alternative architectures. In part 2 we dive deeper into these three architectures to better understand how these filters work. We will also examine the HLS optimizations we applied and the resulting benefits. Example Filter Bank Review Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample rate (red) has been chosen and the output sample rate is downsampled by 16 (green).