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Cypress Semiconductor Corp. has launched a programmable product for data communication over existing power lines. The Powerline Communication product leverages the programmable analog and digital resources of Cypress's PSoC programmable system-on-a-chip architecture. It integrates multiple functions beyond communication, such as power measurement, system management and LCD drive. In addition to its flexibility and integration, the product offers greater than 97% packet success rates without retries and 100% success rates with retries built into the solution's coding, according to Cypress. It also offers the flexibility to communicate over high-voltage and low-voltage power lines for lighting and industrial control, home automation, automatic meter reading and smart energy management applications.

Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them. "There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec. On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.

(Nanowerk News) Scientists at the University of Glasgow have devised a molecular 'LEGO toolkit' which can be used to assemble a vast number of new and functional chemical compounds. Using molecules as building blocks they have been able to construct a molecular scaffold based on tiny (nano-scale) storage cubes. This new ‘designer route’ opens the door to many new compounds that, potentially, are able to act as the ion sensors, storage devices, and catalysts of the future. Researchers within the Department of Chemistry created hollow cube-based frameworks from polyoxometalates (POMs) – complex compounds made from metal and oxygen atoms – which stick together like LEGO bricks meaning a whole range of well-defined architectures can be developed with great ease ("Face-directed self-assembly of an electronically active Archimedean polyoxometalate architecture").

The FPGAs referenced in these articles have complex dedicated I/O circuitries that are primarily designed to support external memory interfaces. The ALTMEMPHY megafunction is designed to support the most common memory standards, such as the DDR and DDR 2 SDRAM and QDR II+/QDR II SRAM (in a burst length of 4) interfaces. The ALTMEMPHY megafunction should be used whenever possible as it is beneficial to use the IP and timing closure methodologies used with these FPGAs, which enables users not to have to create this function manually as compared with using the ALTDLL and ALTDQ_DQS solution. However, the ALTMEMPHY megafunction does not support other external memory standards such as Mobile DDR, QDR II+/QDR II SRAM (in burst length of 2) or customized DDR and DDR 2 SDRAM external memory standards. For these scenarios, use the ALTDLL and ALTDQ_DQS megafunctions to access the FPGA architecture and build a custom external memory interface.

Walking, swallowing, respiration and many other key functions in humans and other animals are controlled by Central Pattern Generators (CPGs). In essence, CPGs are small, autonomous neural networks that produce rhythmic outputs, usually found in animal's spinal cords rather than their brains. Their relative simplicity and obvious success in biological systems has led to some success in using CPGs in robotics. However, current systems are restricted to very simple CPGs (e.g., restricted to a single walking gait). A recent breakthrough at the BCCN at the University of Göttingen, Germany has now allowed to achieve 11 basic behavioral patterns (various gaits, orienting, taxis, self-protection) from a single CPG, closing in on the 10–20 different basic behavioral patterns found in a typical cockroach. The trick: Work with a chaotic, rather than a stable periodic CPG regime. For more on CPGs, listen to the latest episode of the Robots podcast on Chaos Control, which interviews Poramate Manoonpong, one of the lead researchers in Göttingen, and Alex Pitti from the University of Tokyo who uses chaos controllers that can synchronize to the dynamics of the body they are controlling.

Orchard will create shared components for building ASP.NET applications and extensions, and specific applications that leverage these components to meet the needs of end-users, scripters, and developers. Additionally, we seek to create partnerships with existing application authors to help them achieve their goals. Orchard is delivered as part of the ASP.NET Open Source Gallery under the CodePlex Foundation. It is licensed under a New BSD license, which is approved by the OSI. The intended output of the Orchard project is three-fold: Individual .NET-based applications that appeal to end-users , scripters, and developers A set of re-usable components that makes it easy to build such applications A vibrant community to help define these applications and extensions In the near term, the Orchard project is focused on delivering a .NET-based CMS application that will allow users to rapidly create content-driven Websites, and an extensibility framework that will allow developers and customizers to provide additional functionality through extensions and themes. Erik Porter and Nathan Heskew are two of the developers of Orchard. Do they look familiar? Sure they do. They used to be devs on the C9 team.

Analog Devices, Inc., has introduced a pair of Class-D audio amplifiers for smart phones, GPS units and other handheld electronics where premium sound quality offers a major competitive advantage. The SSM2375 and SSM2380 amplifiers provide audio system designers with the option of fixed or programmable gain settings combined with low noise and superior audio performance. The SSM2380 low-power, stereo Class-D amplifier is the first in its class to incorporate an I²C interface, which allows gain stages to be set from 1 dB to 24 dB (plus mute) in 47 distinct steps with no other external components required. The programmable interface also enables independent L/R channel shutdown, a variable low-EMI (electro-magnetic interference) emission control mode, and programmable ALC (automatic level control) functions for speaker protection. The SSM2380 achieves a 100-dB SNR (signal-to-noise ratio) and extends battery life by achieving 93 percent power efficiency at 5 V while running at 1.4 W into an 8-ohm speaker.

Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains. While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures. But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps. In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.

NAMO (Novel Articulated MObile platform)  is a humanoid robot built by The Institute of Field Robotics (FIBO) at King Mongkut’s University of Technology Thonburi in Thailand. FIBO is active in the RoboCup scene and have developed a wide range of robot types, including an experimental biped.  NAMO was unveiled on March 29th 2010, serving as FIBO’s mascot as part of the university’s 50 year anniversary celebrations.  NAMO will be used to welcome people to the university and may be deployed at museums.  Given its friendly appearance and functionality, it could be used to research human robot interaction and communication. NAMO is 130cm (4′3″) tall and has 16 degrees of freedom.  It moves on a stable three-wheeled omnidirectional base, and is equipped with a Blackfin camera for its vision system.  It is capable of simple gesture recognition, visually tracks humans or objects of interest automatically, and can speak a few phrases in a child-like voice (in Thai).

Since I wrote a bittorrent client in both Erlang and Haskell, etorrent and combinatorrent respectively, I decided to put up some bait. This might erupt in a language war and “My language is better than yours”, but I feel I am obligated to write something subjective. Here is to woes of programming in Haskell and Erlang.Neither Haskell, nor Erlang was a first language for me. I have programmed serious programs in C, Standard ML, Ocaml, Python, Java and Perl; tasted the cake of Go, Javascript, Scheme and Ruby; and has written substantial stuff in Coq and Twelf. I love static type systems, a bias that will rear its ugly head and breathe fire.I have written Haskell code seriously since 2005 and Erlang code seriously since 2007. I have programmed functionally since 1997 or so. My toilet reading currently is “Categories for the working mathematician” by Mac Lane. Ten years ago it was “ML for the working programmer” by Paulson.Enough about me.

Xilinx Inc. today introduced the architecture for a new Extensible Processing Platform they claim will deliver unrivaled levels of system performance, flexibility and integration to developers of a wide variety of embedded systems. The ARM Cortex-A9 MPCore processor-based platform enables system architects and embedded software developers to apply a combination of serial and parallel processing to address the challenges they face in designing today's embedded systems, which must meet ever-growing demands to perform highly complex functions. The Xilinx Extensible Processing Platform offers embedded systems designers a processor-centric design and development approach for achieving the compute and processing horsepower required to drive tasks involving high-speed access to real-time inputs, high-performance processing and complex digital signal processing - or any combination thereof - needed to meet their application-specific requirements, including lower cost and power.