Electronic Everything!

Icosatetraped does, in fact, mean “twenty-four legged.” I’m not sure how to inject “soft” into that word (icostatetrasquishaped?), but this robot does have 24 soft legs. Or rather, 8 legs are soft (and moving) at any one time, while the other 16 are pressurized to carry the weight of the bot. It can move at about 1 meter per minute, which isn’t especially fast, but who cares, look at all of those little legs go! Made from plastic medical tubing, particle board, a bunch of solenoids, a Mac Mini, and some 24 volt rotary vane compressors salvaged from Gulf War nerve gas detecting equipment, this is about as DIY as it gets, and it’s awesome.

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.

In earlier articles on intelligent sensor design, we saw how valuable they can be to both end users and those who manufacture and sell them. It’s now time to delve more deeply into what it takes to make intelligent sensors work.   The first step in that journey is to develop a solid, intuitive understanding of the principles of digital signal processing(DSP). Unlike many introductory DSP articles and texts, the focus here will be on presenting and using the important concepts rather than deriving them, for the simple reason that addressing the subject in depth is a book-sized, not a chapter-sized, project.

Ted Marena of Lattice Semiconductor Corp., points out that designers of digital systems are familiar with implementing the 'leftovers' of their digital design by using FPGAs and CPLDs to glue together various processors, memories, and standard function components on their printed circuit board. In addition to these digital functions, FPGAs and CPLDs can also implement common analog functions using an LVDS input, a simple resistor capacitor (RC) circuit and some FPGA or CPLD digital logic elements to create an analog to digital converter (ADC).

(Nanowerk News) While the laws of physics weren’t made to be broken, sometimes they need revision. A major current law has been rewritten thanks to the three-port transistor laser, developed by Milton Feng and Nick Holonyak Jr. at the University of Illinois.

ON Semiconductor has expanded its multiplexer product line with devices that are designed to function at high input rates/clock frequencies. The NB6VQ572M, NB6LQ572, NB7L572, NB6L572M, NB7LQ572, NB6LQ572M, NB7VQ58M and NB7V58M mux/fanout devices are targeted at SONET, Gigabit Ethernet, Fiber Channel, backplane and other clock/data distribution applications. The NB6VQ572M and NB6LQ572M differential 4:1 clock/data input multiplexers with 1:2 current mode logic (CML) clock/data fanout buffers operate at up to 6 GHz/8 Gbps from a 1.8 V, 2.5 V or 3.3 V power supply. The new devices have a data dependent jitter of <10 ps and random clock jitter of less than 0.8 ps RMS.

Linear and nonlinear device models are costly and time-consuming to develop. Most compact model parameters are extracted from linear, 50-ohm S-parameters and predicting behavior under extreme nonlinear conditions or non-50 ohm terminations is unreliable. This white paper entitled "X-parameters and Beyond, AWR's Support of PHD and Nonlinear Behavioral Models," provides details on rapidly-emerging nonlinear models and measurement systems and how Thye are employed in AWR's Microwave Office high-frequency design software.

Predicting trends is difficult even by the most connected industry experts, but one trend that's easy to spot is the widespread acceptance of multicore SoC. This is happening for a number of reasons. First, it's been years since the workstation first adopted the multicore processor architecture to solve such issues as increasing performance and power concerns. While the adoption rate in workstations is now saturated and is fully supported by General Purpose OSs (GPOS), the embedded world is just now looking at ways to adopt multicore architecture. Second, several SoC vendors have been providing multicore solutions including Cavium, Freescale, MIPS, and ARM; but up until now, these solutions have been limited to networking and used for performance enhancements rather than for low power. The rest of the embedded industry has had limited hardware options available as low-power design is a driving factor. While the ARM 11 MPCore was ahead of its time, the Cortex-A9 MPCore design is ready for primetime and is gaining acceptance in the embedded marketplace. As a result, SoC vendors have adopted the Cortex-A9 MPCore hardware as a basis for their next generation designs. Over a year ago, Texas Instruments pre-announced their next-generation OMAP designs in the OMAP 4 with a dual-core Cortex-A9 MPCore, scheduled for production in the second-half of 2010. ST Microsystems has pre-announced their next generation consumer devices which will be based on the Cortex A9 MPCore.

A new chink has been found in the cryptographic armor that protects bank transactions, credit-card payments, and other secure Internet traffic. And although programmers have devised a patch for it, clever hackers might still be able to break through. The hack, presented in March at a computer security conference in Dresden, Germany, involves lowering the input voltage on a computer’s cryptography chip set and collecting the errors that leak out when the power-starved chips try and (sometimes) fail to encode messages. Crooks would then use those errors to reconstruct the secret key on which the encryption is based. More important, say the hack’s creators, the same attack could also be performed from afar on stressed systems, such as computer motherboards that run too hot or Web servers that run too fast.

NXP BV (Eindhoven, The Netherlands) has said it will demonstrate a microcontroller based on the ARM Cortex-M4 at the Embedded Systems Conference in San Jose, California. NXP was one of the first companies to license the Cortex-M4 processor core and a chip has been implemented using a low-leakage 90-nm process technology. This enables performance in excess of 150-MHz clock frequency, NXP said. NXP has added proprietary power-down techniques to reduce power consumption. The ESC Silicon Valley demo will show that a 7-channel audio graphic equalizer application processing 32-bit precision audio data requires only 12 MHz of CPU bandwidth using the Cortex-M4 DSP extensions, and 60 MIPs without. The core includes DSP extensions not usually found inside a microcontroller and NXP's implementation are aimed at a broad set of applications including motor control, digital power control and embedded audio.

Breadboarding a new circuit is a key skill and an important step in many projects—especially early on, when you need to move wires around and substitute components. But that very flexibility also makes it easy to knock wires out. Eventually, if your project is a keeper, you’re going to want something with a bit more permanence. Printed circuit boards (PCBs) solve all those shortcomings. But most people don’t even consider translating a one-off project into a PCB design. For one thing, PCB fabrication has traditionally been expensive, viable only in commercial quantities. (One alternative is to do it yourself with etches and silk screens, a messy and time-consuming process.) Also, there are technical constraints involved with PCB designs that are daunting to the casual hobbyist. But it turns out that nowadays you can produce a professional PCB very inexpensively.

March has seen two significant announcements from FPGA start-ups with innovative architectures: Tabula, with their time-domain-multiplexed architecture, and TierLogic, implementing their routing switches in a layer of thin-film transistors. Both approaches promise to significantly reduce the die size and cost of high-end FPGAs. But before these announcements broke, a relatively unnoticed paper at February's International Symposium on FPGAs described what may be the most radical technology of them all: FPGAs using electromechanical relays. No, this is not an early April Fool's joke, nor is it one of those "let's see if anyone will publish this one" academic exercises. The paper presented work by professors and students at the Stanford University departments of electrical engineering and computer science, and researchers at Altera Corp. The work was supported in part by DARPA funding.

Related to the strong demands for virtualization technology, network I/O virtualization has recently become a hot topic and is one of the key topics being discussed at the upcoming Multicore Expo @ ESC. In fact, analyst firm IDC, in a recent white paper titled "Optimizing I/O Virtualization: Preparing the Data Center for Next-Generation Applications", stated that "If I/O is not sufficient, then it could limit all the gains brought about by the virtualization process."

Avnet Electronics Marketing and Xilinx Inc. said they have concluded their five-month, 37-city global X-fest technical seminar series. According to the companies, the free one-day training sessions offered practical, how-to system level design instruction featuring the Spartan-6 and Virtex-6 FPGA families from Xilinx, as well as key enabling technologies from suppliers including Cypress Semiconductor, Intel, Maxim Integrated Products, National Semiconductor, NXP, Texas Instruments and Tyco Electronics. Replays of the events are available online.

How's this for a wedge issue on a slow news week? When Xilinx announced earlier this year that it was changing one of its foundry suppliers from UMC to TSMC for the 28-nm node, it seemed like a blow to differentiation—at least from a process technology standpoint—between Xilinx and Altera, which has been using TSMC for years. But while Xilinx chose to go with TSMC's high-performance/low power process, Altera said this week it is going with TSMC's high-performance process. Altera maintains that customers in the high end communications equipment market are much more concerned about performance than power. Luanne Schirrmeister, senior director of product marketing at Altera, put it this way: "In communications infrastructure, nothing is battery powered. Everything is plugged into a wall."

Intel has announced that is developing a system-on-chip for embedded applications based around its Atom processor core. However, it appears the SoC will be of a fixed design with a PCI Express bus interface to which system-level customers can attach their own or third-party chips. Similarly it appears that Intel will manufacture the system-chip internally rather than allowing a foundry to make the chip, or add its customers' IP to the design. Doug Davis, corporate vice president and general manager of Intel's embedded and communications group, disclosed details of the "Tunnel Creek" SoC during his keynote speech on Wednesday (April 14) at the Intel Developer Forum, in Beijing China.

Let’s face it. Most of the gear you use at work or play has multicore processors in it. Your laptop has them (the CPU itself has two cores, and the dedicated graphics processor has many more). That game console in the living room has still more, and even a high-end smartphone typically has a CPU and graphics core on a single chip. Out of sight but definitely not out of mind–particularly if they cease working–are the servers and high-throughput network routers, all which have numerous multicore processors in them. The multiple cores in these devices work in concert to provide quick responses to user queries or to manage the smooth flow of data throughout the office.

Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains. While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures. But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps. In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.

One of the biggest commercial applications of spintronics in computing to date has been the use of giant magnetoresistance (GMR), the material phenomenon that makes possible the huge storage capacity of today’s hard disk drives. In the awarding of the 2007 Nobel Prize in Physics, GMR was cited as the first big commercial application for nanotechnology. But extending the commercial application of spintronic-enabled systems beyond read heads for HDDs has proven to be a difficult task. One need only look at the seemingly endless travails of NVE Corporation, which in its financial results still shows it greatest revenue growth in contract research as opposed to product sales. While recent research from a team of researchers at Ohio State University and the University of Hamburg in Germany may not turn around the fortunes of spintronics in the short term, it does provide a way to better characterize the spin of electrons and thereby promises better ways of exploiting it for electronics applications. The researchers are reporting in Nature Nanotechnology that they have for the first time been able to create images of the spin direction of electrons.

FPGA devices create compelling business drivers generating a tidal wave of FPGA adoption for the implementation of system PCB designs. Obviously, the time to market advantages and capacity/performance characteristics of FPGA devices have delivered on the promise for a viable alternative to more capital resource intensive custom IC/ASIC solutions as well as a successful consolidation vehicle for standard "off the shelf" components in system design creation.