Ozmo Devices, the leading provider of low-power Wi-Fi Personal Area Network (Wi-Fi PAN) solutions, announced today that it started sampling its OZMO2000 chip to select peripheral manufacturers.  This is the first Wi-Fi solution to overcome the battery life, cost and compatibility issues that have limited the broad adoption of Wi-Fi for HID (human interface device) applications.  The OZMO2000 is currently available for use in Wi-Fi mouse, keyboard and remote control designs.  Furthermore, the solution is compatible with all Wi-Fi-enabled notebooks and desktops that are compatible with Windows 7.

It is no secret that field-programmable gate arrays (FPGAs) are getting bigger and more complex all the time. The fabrication process creates smaller transistors and makes more dense chips packing more digital processing per nanometer. Engineers love to see advancement because it means they can do more with modern silicon, and many times NI LabVIEW FPGA Module technology helps by abstracting the complexity to a higher level so that engineers can more smoothly take advantage of these improvements.  Unfortunately, there is one issue with FPGAs that continues to be a time sink and only gets worse with denser FPGAs: compilation time.

High Level Synthesis Architectural Optimization Basics In part 1 of this article we introduced basic filter bank theory and used the Synplify DSP High Level Synthesis (HLS) tool to implement an example filter bank into three alternative architectures. In part 2 we dive deeper into these three architectures to better understand how these filters work. We will also examine the HLS optimizations we applied and the resulting benefits. Example Filter Bank Review Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample rate (red) has been chosen and the output sample rate is downsampled by 16 (green).

TTE Systems' RapidiTTy IDE provides a self-contained environment for developers who wish to create "time-triggered" microcontroller software in order to improve overall system reliability. RapidiTTy (Figure 1, below) is intended to address deeply-embedded applications including control and monitoring operations in medical, defence, automotive and industrial sectors, as well as in white and brown goods.

A shielded transformer is a two-winding transformer, usually delta"star connected and serves the following purposes: Voltage transformation from the distribution voltage to the equipment's utilization voltage. Converting a 3-wire input power to a 4-wire output thereby deriving a separate stable neutral for the power supply wiring going to sensitive equipment. Keeping third and its multiple harmonics away from sensitive equipment by allowing their free circulation in the delta winding. Softening of high-frequency noise from the input side by the natural inductance

In traditional short-haul microwave transmission (that is, line-of-sight microwave transmissions operating in the 18 GHz and 23 GHz radio bands),RF design engineers typically are concerned with signal aspects such as fade margins, signal reflections, multipath signals, and so forth. Like an accountant seeking to balance a financial spreadsheet, an RF design engineer normally creates an RF budget table, expressed in decibels (dB), in order to establish a wireless design. Aspects like transmit power and antenna gain are registered in the assets (or plus) column, and free space attenuation, antenna alignment, and atmospheric losses are noted in the liabilities (or minus) column. The goal is to achieve a positive net signal strength adequate to support the wireless path(s) called for in the design.

The center piece of our toolset is the software integrated development environment or IDE. MPLAB IDE has enjoyed many years of evolution cracking Microchip’s popular catalogue of micro controllers and digital signal controllers. This presentation will cover these topics. Look at MPLAB and its components. An MPLAB IDE overview, MPLAB’s hardware components including starter kits and demonstration and evaluation kits and finally we attempt to answer the question why use Microchip tools.

In addition to voice connectivity, digital cellular wireless networks such as GSM and its enhancement, GSM-EDGE, can now provide increased data speeds up to a (theoretical) limit of 384ﾠKbps. Third generation mobile networks, such as CDMA2000 and WCDMA or UMTS (Universal Mobile Telecommunications Standards) and TD-SCDMA (China only) are currently being deployed worldwide. These systems offer services such as video streaming, Internet browsing and, by using a technique called High Speed Packet Access (HSPA), they can in theory deliver downlink speeds up to 14,4 Mbps.

Earlier in this series, we touched on one problem that can arise when sampling an analog signal, namely the problem of aliasing. There are three other issues with signal sampling to which we now turn our attention: digitization effects, finite register length effects, and oversampling. So far, weve assumed that all of the signals were measuring are continuous analog values; i.e., our measurements are completely accurate. Even in the cases in which we have noise, the underlying assumption is that the measurement itself, for example the noisy sensor output voltage, is known precisely.

We’re all familiar with the general idea of a filter: it removes something that we don’t want from something we do want. Coffee filters that pass the liquid coffee but retain the grounds or air filters that pass clean air but trap the dust and other pollutants are two common examples of mechanical filters in everyday life. That same concept can be applied to noisy electrical signals to pass through the “true” signal of interest while blocking the undesirable noise signal. Looking at Figure 2.5c below, imagine for a moment that the signal of interest is in the lower-frequency region and that the noise signal is in the higher-frequency region. Ideally, we’d like to be able to get rid of that high-frequency noise, leaving just the signal component that we want.

In earlier articles on intelligent sensor design, we saw how valuable they can be to both end users and those who manufacture and sell them. It’s now time to delve more deeply into what it takes to make intelligent sensors work.   The first step in that journey is to develop a solid, intuitive understanding of the principles of digital signal processing(DSP). Unlike many introductory DSP articles and texts, the focus here will be on presenting and using the important concepts rather than deriving them, for the simple reason that addressing the subject in depth is a book-sized, not a chapter-sized, project.

Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before.

Field programmable gate arrays (FPGAs) present an efficient and inexpensive alternative when it comes to implementing complete embedded systems along with important peripheral functions. The reconfigurable logic circuitry of an FPGA offers tremendous flexibility. A lesser known feature is that the outputs of a digital FPGA also permit various analogue applications.

National Instruments has released a vision module for the PXI platform that provides a high-performance parallel processing architecture for hardware-defined timing, control and image pre-processing. The NI 1483 Camera Link adapter module, in combination with an NI FlexRIO field-programmable gate array (FPGA) board, offers a solution for embedding vision and control algorithms directly on FPGAs which are used to process and analyse an image in real time with little to no CPU intervention. The FPGAs can be used to perform operations by pixel, line and region of interest. They can implement many image processing algorithms that are inherently parallel, including fast Fourier transforms (FFTs), thresholding and filtering.

Menta SAS and LIRMM have taped out what they believe is the of worlds first MRAM-based FPGA which has patent-protected circuitry enabling compact integration of MRAM and embedded-FPGA solutions. Researchers at the Montpellier Laboratory of Informatics, Robotics and Microelectronics (LIRMM), in France, claimed in October that they had developed a FPGA circuit based on non volatile resistive memory cell.

Given the maturity of MOSFETs, selecting one for your next design may seem deceptively simple. Engineers are familiar with the figures of merit on a MOSFET data sheet. Selecting a MOSFET requires the engineer to use their expertise in scrutinizing different specifications for individual applications. In an application such as a load switch in a server power supply, the switching aspects of a MOSFET matter little because the MOSFET is on almost 100% of the time. The on resistance (RDS(ON)) may be the key figure of merit in such an application. Still other applications, including switching power supplies, use MOSFETs as active switches, and cause the engineer to value other MOSFET performance parameters. Let us consider some applications and their prioritization of MOSFET specifications.

Recent advances in the size and performance of FPGAs, coupled with advantages in time-to-market, field-reconfigurability and lower up-front costs, make FPGAs ideally suited to a wide range of commercial and defense applications [6]. In addition, FPGAs generality and reconfigurability provide important protections against the introduction of Trojan horses during semiconductor manufacturing process[8]. As a result, FPGA applications increasingly involve highly-sensitive intellectual property and trade-secrets, as well as cryptographic keys and algorithms [7].

By using a simple value process it is possible to speed up the analysis and help identify the best approach to take when developing a constant current regulation scheme for automotive interior LED lighting systems. Various approaches exist to address this particular design challenge that may result in a slowdown of the design process while engineering analysis can be performed to consider the advantages and disadvantages of the different options.

In separate keynote addresses in Silicon Valley, two Internet pioneers gave different takes on the future of the network of networks Monday (May 24). Vint Cerf, co-developer of the Net's TCP/IP protocol, shared his thoughts with developers of the smart electric grid, seen as a massive embedded extension to the Internet. Larry Roberts, who helped launch the forerunner of the Internet, explained his ideas for remedying the growing congestion that plagues the Web today. Smart grid developers can learn from the lessons of the Internet, Cerf told attendees at Connectivity Week here. They should follow the model of the Net in creating a layered architecture with plenty of room for flexibility in areas that cannot be anticipated today, he said in a keynote at Connectivity Week.

Sony Corp. has developed a highly flexible OLED display that can be rolled around a pencil and continue to operate. The 4.1-inch diagonal isplay is 80-microns thick and offers 432 by 240 by RGB pixels resolution at 121 pixels per inch. It is an organic LED full color display driven by an organic thin-film transistor matrix.