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One of the biggest commercial applications of spintronics in computing to date has been the use of giant magnetoresistance (GMR), the material phenomenon that makes possible the huge storage capacity of today’s hard disk drives. in the awarding of the 2007 Nobel Prize in Physics, GMR was cited as the first big commercial application for nanotechnology. But extending the commercial application of spintronic-enabled systems beyond read heads for HDDs has proven to be a difficult task. One need only look at the seemingly endless travails of NVE Corporation, which in its financial results still shows it greatest revenue growth in contract research as opposed to product sales. While recent research from a team of researchers at Ohio State University and the University of Hamburg in Germany may not turn around the fortunes of spintronics in the short term, it does provide a way to better characterize the spin of electrons and thereby promises better ways of exploiting it for electronics applications. The researchers are reporting in Nature Nanotechnology that they have for the first time been able to create images of the spin direction of electrons.

In traditional short-haul microwave transmission (that is, lIne-of-sight microwave transmissions operatIng In the 18 GHz and 23 GHz radio bands),RF design engIneers typically are concerned with signal aspects such as fade margIns, signal reflections, multipath signals, and so forth. Like an accountant seekIng to balance a fInancial spreadsheet, an RF design engIneer normally creates an RF budget table, expressed In decibels (dB), In order to establish a wireless design. Aspects like transmit power and antenna gaIn are registered In the assets (or plus) column, and free space attenuation, antenna alignment, and atmospheric losses are noted In the liabilities (or mInus) column. The goal is to achieve a positive net signal strength adequate to support the wireless path(s) called for In the design.

Ever since graphene was first produced in a lab at the University of Manchester in 2004, researchers around the world have been fascinated with its potential in electronics applications. Graphene possessed all the benefits of carbon nanotubes (CNTs), namely its charged-carrier mobility, but it didn’t have any of the down sides, such as CNTs’ need for different processing techniques than silicon and the intrinsic difficulty of creating interconnects for CNTs. But all was not easy for applying graphene to electronics applications. One of the fundamental problems for graphene was its lack of a band gap, which left it with a very low on-off ratio measured at about 10 as compared to in the 100s for silicon. Now this fundamental hurdle has been overcome. Based on research led by Phaedon Avouris at IBM’s IBM T.J. Watson Research Center, Yorktown Heights, New York, IBM is reporting that they have created a significant band gap in graphene.

I remember when, a decade ago, Kevin Warwick, a professor at the University of Reading, in the U.K., implanted a radio chip in his own arm. The feat caused quite a stir. The implant allowed him to operate doors, lights, and computers without touching anything. On a second version of the project he could even control an electric wheelchair and produce artificial sensations in his brain using the implanted chip. Warwick had become, in his own words, a cyborg. The idea of a cyborg -- a human-machine hybrid -- is common in science fiction and although the term dates back to the 1960s it still generates a lot of curiosity. I often hear people asking, When will we become cyborgs? When will humans and machines merge? Although some researchers might have specific time frames in mind, I think a better answer is: It's already happening. When we look back at the history of technology, we tend to see distinct periods -- before the PC and after the PC, before the internet and after the internet, and so forth -- but in reality most technological advances unfold slowly and gradually. That's particularly true with the technologies that are allowing us to modify and enhance our bodies.

Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. in this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. in a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.

The consumer handheld market is growing by leaps and bounds. With more processing power and increased support for more applications, portable products are cross-pollinating with traditional computing systems even as the product life cycle has decreased considerably in this market segment. As a result, especially in this era of economic slowdown, it is imperative that new products meet the time-to-market window to gain maximum acceptance. A decrease in product life cycles requires a reduced development cycle and an increased emphasis on reusability and reprogrammability. The emerging handheld market is also seeing interesting trends in which each individual device in a family has lower volumes but there is more customization across the series of devices, effectively upping the total unit volumes. The key challenge then becomes how to develop a system that is widely reusable and also customizable. These requirements have led designers increasingly to turn to the FPGA for handheld-product development. The FPGA has become more powerful and feature-rich, while gate counts, area and frequency have increased. FPGA development and turnaround cycles are considerably shorter than those of custom ASICs, and the added advantage of reprogrammability can make the FPGA a more compelling solution for handheld embedded systems.

Power and energy are key design considerations across a spectrum of computing solutions, from supercomputers and data centers to handheld phones and other mobile computers. A large body of work focuses on managing power and improving energy efficiency. While prior work is easily summarized in two words—"Avoid waste!"—the challenge is figuring out where and why waste happens and determining how to avoid it. in this article, I discuss how, at a general level, many inefficiencies, or waste, stem from the inherent way system architects address the complex trade-offs in the system-design process. I discuss common design practices that lead to power inefficiencies in typical systems and provide an intuitive categorization of high-level approaches to addressing them. The goal is to provide practitioners—whether in systems, packaging, algorithms, user interfaces, or databases—a set of tools, or "recipes," to systematically reason about and optimize power in their respective domains.

In separate keynote addresses In Silicon Valley, two Internet pioneers gave different takes on the future of the network of networks Monday (May 24). VInt Cerf, co-developer of the Net's TCP/IP protocol, shared his thoughts with developers of the smart electric grid, seen as a massive embedded extension to the Internet. Larry Roberts, who helped launch the forerunner of the Internet, explaIned his ideas for remedyIng the growIng congestion that plagues the Web today. Smart grid developers can learn from the lessons of the Internet, Cerf told attendees at Connectivity Week here. They should follow the model of the Net In creatIng a layered architecture with plenty of room for flexibility In areas that cannot be anticipated today, he said In a keynote at Connectivity Week.

Earlier in this series, we touched on one problem that can arise when sampling an analog signal, namely the problem of aliasing. There are three other issues with signal sampling to which we now turn our attention: digitization effects, finite register length effects, and oversampling. So far, weve assumed that all of the signals were measuring are continuous analog values; i.e., our measurements are completely accurate. Even in the cases in which we have noise, the underlying assumption is that the measurement itself, for example the noisy sensor output voltage, is known precisely.

We’re all familiar with the general idea of a filter: it removes something that we don’t want from something we do want. Coffee filters that pass the liquid coffee but retain the grounds or air filters that pass clean air but trap the dust and other pollutants are two common examples of mechanical filters in everyday life. That same concept can be applied to noisy electrical signals to pass through the “true” signal of interest while blocking the undesirable noise signal. Looking at Figure 2.5c below, imagine for a moment that the signal of interest is in the lower-frequency region and that the noise signal is in the higher-frequency region. Ideally, we’d like to be able to get rid of that high-frequency noise, leaving just the signal component that we want.