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Cooking is an art sometimes forgotten in the robotics world, but James, the PR2 robot, and Rosie, another robot from CoTeSys (Cognition for Technical Systems) in Munich have joined forces to show that robots can be of great use in the kitchen as well. They made some pretty successful-looking pancakes and used various tools around the Assisted Kitchen to show off their skills. The main chef in the experiment was Rosie, who used her broad arms and high levels of dexterity to flip and cook the pancakes. As you can see in the video, she is a bit on the slow side, but she’s also extra careful and gets it done right. She is capable of adjusting the way she pours the batter based on the weight of the bowl, demonstrating some impressive planning and a good use of her sensors, which allow the bot to recognize how much batter she has already poured.

Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them. "There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec. On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.

How's this for a wedge issue on a slow news week? When Xilinx announced earlier this year that it was changing one of its foundry suppliers from UMC to TSMC for the 28-nm node, it seemed like a blow to differentiation—at least from a process technology standpoint—between Xilinx and Altera, which has been using TSMC for years. But while Xilinx chose to go with TSMC's high-performance/low power process, Altera said this week it is going with TSMC's high-performance process. Altera maintains that customers in the high end communications equipment market are much more concerned about performance than power. Luanne Schirrmeister, senior director of product marketing at Altera, put it this way: "In communications infrastructure, nothing is battery powered. Everything is plugged into a wall."

As I noted last week, US Federal Bureau of Investigation (FBI) Director Robert Mueller told the US House Appropriations Committee’s Subcommittee on Commerce, Justice, Science, and Related Agencies that the follow-on to the notoriously failed $170 million Virtual Case File program called Sentinel would once again slip its schedule and cost targets. The latest cost estimate is in excess of $481 million with a total program slip now of some two years and counting.    Director Mueller told the House Committee that the FBI decided to suspend work on Sentinel in early March to correct some "minor" technical issues and make some design changes. These issues included, according to the New York Times, "slow response times, awkward display pages and screen print that was too small."