Simple mathematical analysis shows that the best answer to address this problem is to select a CR ratio QGD/QGS1 that is less than 1. Other factors to consider for preventing C dv/dt induced turn-on include low driver-sinking impedance (<1 Ώ), a FET design with intrinsically low RG, an externally-applied G-S capacitor and Q2 packages that minimize parasitics and voltage ringing.
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