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High Level Synthesis Architectural Optimization Basics In part 1 of this article we introduced basic filter bank theory and used the Synplify DSP High Level Synthesis (HLS) tool to implement an example filter bank into three alternative architectures. In part 2 we dive deeper into these three architectures to better understand how these filters work. We will also examine the HLS optimizations we applied and the resulting benefits. Example Filter Bank Review Before we proceed, let's quickly review our filter bank example. Our example, shown in Figure 1, is a size 16 DFT filter bank. The color scheme shows the sample rate change where a 16 MHz input sample rate (red) has been chosen and the output sample rate is downsampled by 16 (green).

Rube Goldberg couldn’t have designed a more elegant confluence of convoluted causal relationships.  Start analyzing the perplexing paradox of the FPGA synthesis market and each link of the chain reveals a bizarre force vector that eventually doubles back onto itself into an unlikely equilibrium that miraculously has held stable for a full decade despite disruptive forces of epic proportions. For over a decade now, Synplify has navigated these waters and has continued to survive and thrive through the unlikeliest of conditions.  Now in the hands of EDA giant Synopsys, the Synplify family of FPGA synthesis tools continues to evolve - with a major upgrade this fall.  When you put a digital design into an FPGA, there are two technologies that determine whether your design fits or doesn’t fit, whether it meets your timing constraints or does not, whether the power consumption will be within your limits (or those of the FPGA), or whether it fails completely, leaving your project at the mercy of major mulligans.   Those two technologies are synthesis and place-and-route. 

Tigal announced the VoiceGP family of products under its VeeaR brand of voice and speech recognition products. The product family consists of the VoiceGP module and two development kits with bundled development software. It combines all the hardware and software required for easy and cost effective development and implementation of speech synthesis and multi-language speaker independent and speaker dependent speech recognition capabilities to virtually any application, says the manufacturer. The VoiceGP Module is based on Sensory's RSC-4128 mixed signal processor. Its 42x72mm footprint and two 28-pin connectors with 2.54mm pin spacing make the module breadboard friendly and suitable for prototype boards.

Have you ever written code that behaves correctly under a simulator only to have intermittent failures in the field? Or maybe your code no longer functions properly when you compile with a newer version of your tool chain. You review your test bench and verify 100 percent complete test coverage and that all tests have passed with no errors--yet the problem stubbornly remains. While designers understandably place great emphasis on coding and simulation, they often have only a nodding acquaintance with the internal workings of the silicon within an FPGA. As a result, incorrect logic synthesis and timing problems, rather than logic errors, are the cause of most logic failures. But writing FPGA code that creates predictable, reliable logic is simple if designers take the right steps. In FPGA design, logic synthesis and related timing closure occur during compilation. And many things, including I/O cell structure, asynchronous logic and timing constraints, can have a big impact on the compilation process, varying results with each pass through the tool chain. Let's take a closer look at ways to eliminate these variances to better and more quickly achieve timing closure.

The latest episode of the Robots Podcast looks at the following scenario: Imagine being able to throw a hand-full of smart matter in a tank full of liquid and then pulling out a ready-to-use wrench once the matter has assembled. This is the vision of this episode's guests Michael Tolley and Jonas Neubert from the Computational Synthesis Laboratory run by Hod Lipson at Cornell University, NY. Tolley and Neubert give an introduction into Programmable Matter and then present their research on stochastic assembly of matter in fluid, including both simulation (see video above) and real-world implementation. Read on or tune in!

GetRobo has pointed out a new website by Francisco Paz, which focuses on his experience building an open source personal robot called Qbo.  From the few images on the site Qbo looks remarkably well made and quite similar to NEC’s PaPeRo, meaning it might be used to experiment with image processing, speech recognition, speech synthesis, and (assuming it has wheels) obstacle detection and SLAM.  He also mentions in his blog some of the open source software that’s out in the wild such as OpenCV, Festival, and Sphinx, which would allow you to do some of that.

Robots might one day trace the origin of their consciousness to recent experiments aimed at instilling them with the ability to reflect on their own thinking. Although granting machines self-awareness might seem more like the stuff of science fiction than science, there are solid practical reasons for doing so, explains roboticist Hod Lipson at Cornell University's Computational Synthesis Laboratory.