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The Energy, Power, Control, and Networks (EPCN) Program supports innovative research in modeling, optimization, learning, adaptation, and control of networked multi-agent systems, higher-level decision making, and dynamic resource allocation, as well as risk management in the presence of uncertainty, sub-system failures, and stochastic disturbances. EPCN also invests in novel machine learning algorithms and analysis, adaptive dynamic programming, brain-like networked architectures performing real-time learning, and neuromorphic engineering. EPCN's goal is to encourage research on emerging technologies and applications including energy, transportation, robotics, and biomedical devices & systems. EPCN also emphasizes electric power systems, including generation, transmission, storage, and integration of renewable energy sources into the grid; power electronics and drives; battery management systems; hybrid and electric vehicles; and understanding of the interplay of power systems with associated regulatory & economic structures and with consumer behavior.

The confluence of transistor scaling, increases in the number of architecture designs per process generation, the slowing of clock frequency growth, and recent success in research exploiting thread-level parallelism (TLP) and data-level parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future. The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) "microarchitecture turbo" techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements that continue the trends characterized by Moore's Law.

The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) "microarchitecture turbo" techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements that continue the trends characterized by Moore's Law.

This program seeks to accelerate fundamental, broad-based research on wireless-specific machine learning (ML) techniques, towards a new wireless system and architecture design, which can dynamically access shared spectrum, efficiently operate with limited radio and network resources, and scale to address the diverse and stringent quality-of-service requirements of future wireless applications. In parallel, this program also targets research on reliable distributed ML by addressing the challenge of computation over wireless edge networks to enable ML for wireless and future applications. Model-based approaches for designing the wireless network stack have proven quite efficient in delivering the networks in wide use today; research enabled by this program is expected to identify realistic problems that can be best solved by ML and to address fundamental questions about expected improvements from using ML over model-based methods.

The confluence of transistor scaling, increases in the number of architecture designs per process generation, the slowing of clock frequency growth, and recent success in research exploiting Thread Level Parallelism (TLP) and Data Level Parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future. The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) "microarchitecture turbo" techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements to continue the cadence promised by Moore's Law.

The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC). This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures. Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) "microarchitecture turbo" techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation. Advances in these areas promise to provide significant performance improvements that continue the trends characterized by Moore's Law.