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TechOnline | FPGA Design Methods for Fast Turn Around - 0 views

  • Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate mark. With designs of this magnitude, the need for fast flows has never been greater. At the same time, designers are seeking rapid feedback on their ASIC or FPGA designs by implementing quick prototypes or initial designs on FPGA-based boards. These prototypes or designs allow designers to start development, verification and debug of the design—in the context of system software and hardware—and also to fine tune algorithms in the design architecture. Quick and intuitive debug iterations to incorporate fixes are of great value. The ability to perform design updates that don't completely uproot all parts of the design that have already been verified is also a bonus! Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.
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TechOnline | FPGA Design Methods for Fast Turn Around - 0 views

  • Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate mark. With designs of this magnitude, the need for fast flows has never been greater. At the same time, designers are seeking rapid feedback on their ASIC or FPGA designs by implementing quick prototypes or initial designs on FPGA-based boards. These prototypes or designs allow designers to start development, verification and debug of the design—in the context of system software and hardware—and also to fine tune algorithms in the design architecture. Quick and intuitive debug iterations to incorporate fixes are of great value. The ability to perform design updates that don't completely uproot all parts of the design that have already been verified is also a bonus! Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.
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How to achieve timing closure in large, complex FPGA designs - 0 views

  • This article features an example chapter from a new *Hot-off-the-Press* book on FPGA Design that just recently hit the streets in August 2010. This chapter is reproduced here with the kind permission of the publisher – Springer. This book -- FPGA Design: Best Practices for Team-Based Design -- describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed.
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How to Cheat at Securing a Wireless Network--Wireless Network Design--Part V - 0 views

  • In traditional short-haul microwave transmission (that is, line-of-sight microwave transmissions operating in the 18 GHz and 23 GHz radio bands),RF design engineers typically are concerned with signal aspects such as fade margins, signal reflections, multipath signals, and so forth. Like an accountant seeking to balance a financial spreadsheet, an RF design engineer normally creates an RF budget table, expressed in decibels (dB), in order to establish a wireless design. Aspects like transmit power and antenna gain are registered in the assets (or plus) column, and free space attenuation, antenna alignment, and atmospheric losses are noted in the liabilities (or minus) column. The goal is to achieve a positive net signal strength adequate to support the wireless path(s) called for in the design.
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Think it - Draw it - Build it - 0 views

  • Embedded systems designers deserve better than the feature-lacking point-tools available today. Embedded designs should be more than a collection of microcontrollers and discrete components, pulled together by board design tools and software development environments that are not aware of each other presence, let alone integrated together. Programmable devices are not new. Embedded software is older than most of us! And a lot of embedded design is highly focused on specific interaction between the software and peripherals. So why do we still not have tools that bring all this together and make our lives easier and more productive?
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National Instruments Introduces Multisim 11, the Latest Version of Circuit Simulation S... - 0 views

  • Multisim 11 is the latest version of its circuit simulation software, with specialized editions for both hands-on learning and professional circuit design. The easy-to-use Multisim software delivers a graphical approach that abstracts the complexities of traditional circuit simulation, helping educators, students and engineers employ advanced circuit analysis technology. The academic edition of Multisim 11 incorporates specialized teaching features and is complemented by circuits textbooks and courseware. This integrated system helps educators engage students and reinforce circuit theory with an interactive, hands-on approach to investigating circuit behavior. Multisim 11 Professional helps engineers optimize circuit designs, minimize errors and reduce prototype iterations. When combined with the new NI Ultiboard 11 layout and routing software, Multisim provides engineers a cost-effective, end-to-end prototyping platform. Its integration with NI LabVIEW measurement software also helps engineers define custom analyses to improve design validation…
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IEEE Spectrum: Design Challenges Loom for 3-D Chips - 0 views

  • Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them. "There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec. On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.
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WEBENCH® Designer Tools | National Semiconductor - 0 views

  • With the introduction of the WEBENCH Online Design Environment in 1999, National Semiconductor made it possible for design engineers to create a reliable power supply circuit over the internet in minutes. The user specified the circuit performance and the WEBENCH Toolset delivered. Today, WEBENCH Designer creates and presents all of the possible power, lighting, or sensing circuits that meet a design requirement in seconds. This enables the user to make value based comparisons at a system and supply chain level before a design is committed. This expert analysis is not possible anywhere else.
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Sunlight Labs: Blog - ClearMaps: A Mapping Framework for Data Visualization - 0 views

  • Despite the recent explosion of web based cartography tools, making effective maps for data visualization remains a challenge. While tools like Google Maps are great for helping navigate the world they are often poorly suited for thematic mapping, as many features like roads and cities only get in the way of telling compelling stories with data. In fact, even the distance between places can be a distraction – who cares how far away Alaska is when the goal is to make a simple comparison between US states? To help overcome some of the limitations with existing mapping tools Sunlight Lab is releasing ClearMaps, an ActionScript framework for interactive cartographic visualization. In addition to giving designers and developers more control over presentation the project aims to address some of the common technical challenges faced when building interactive, data driven maps for the web. ClearMaps is designed as a lightweight, flexible set of tools for building complex data visualizations. It is a framework not a plug-and-play component (though it could be a starting point for those wishing to make reusable tools).
  • Despite the recent explosion of web based cartography tools, making effective maps for data visualization remains a challenge. While tools like Google Maps are great for helping navigate the world they are often poorly suited for thematic mapping, as many features like roads and cities only get in the way of telling compelling stories with data. In fact, even the distance between places can be a distraction – who cares how far away Alaska is when the goal is to make a simple comparison between US states? To help overcome some of the limitations with existing mapping tools Sunlight Lab is releasing ClearMaps, an ActionScript framework for interactive cartographic visualization. In addition to giving designers and developers more control over presentation the project aims to address some of the common technical challenges faced when building interactive, data driven maps for the web. ClearMaps is designed as a lightweight, flexible set of tools for building complex data visualizations. It is a framework not a plug-and-play component (though it could be a starting point for those wishing to make reusable tools).
  • Despite the recent explosion of web based cartography tools, making effective maps for data visualization remains a challenge. While tools like Google Maps are great for helping navigate the world they are often poorly suited for thematic mapping, as many features like roads and cities only get in the way of telling compelling stories with data. In fact, even the distance between places can be a distraction – who cares how far away Alaska is when the goal is to make a simple comparison between US states? To help overcome some of the limitations with existing mapping tools Sunlight Lab is releasing ClearMaps, an ActionScript framework for interactive cartographic visualization. In addition to giving designers and developers more control over presentation the project aims to address some of the common technical challenges faced when building interactive, data driven maps for the web. ClearMaps is designed as a lightweight, flexible set of tools for building complex data visualizations. It is a framework not a plug-and-play component (though it could be a starting point for those wishing to make reusable tools).
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SurfaceCube: Design Thinking for Natural User Interfaces | Inside Out | Channel 9 - 0 views

  • Microsoft Surface is a prime example of how natural user interfaces can change the way we interact with computers. As designers and developers, one challenge with creating natural user interfaces for multi-touch devices such as Microsoft Surface or Windows 7 is getting around the old ways of thinking and old habits for interface design. Joshua Blake from InfoStrat decided to tackle this problem by creating SurfaceCube. SurfaceCube is a simple 3-D puzzle game for Microsoft Surface which he designed to illustrate as many as the Surface Interaction Guidelines as possible. I had the opportunity to sit down with Joshua and discuss SurfaceCube and the thinking behind some really interesting design decisions that makes it stand out as a natural user interface. We also briefly discuss Joshua’s upcoming book about natural user interfaces and multi-touch development, Multitouch on Windows: NUI Development with WPF and Silverlight, due Fall 2010 (since recording this interview, the book titled was updated). As a special offer to Channel 9 readers, you can use the following coupon to order the book through the Manning Early Access Program and read the chapters as Josh writes them. Coupon code channel9y is good for 35% off Multitouch on Windows: NUI Development with WPF and Silverlight when ordered through manning.com, and expires on April 24, 2010.
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Lattice Diamond - 0 views

  • Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before.
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・e-nuvo HUMANOID - 0 views

  • The Nippon Institute of Technology, with Harada Vehicle Design, ZMP, and ZNUG Design, have developed a humanoid robot about the size of an elementary school student for educational purposes.  The university adopted 35 of ZMP’s e-nuvo WALK robots in 2004 for a 1:1 student-robot ratio.  Whereas the e-nuvo WALK (the educational version of NUVO) is quite small, the new robot is tall enough to interact with its environment in a more meaningful way.  Students will demonstrate the robot at elementary and junior high schools, as well as care facilities.  The goal is to improve student learning by raising awareness of bipedal robot technology and its connection to math and physics, while also giving them hands-on experience with the bot.  Additionally, by visiting care facilities the university students will come to understand the real-world needs and applications for robots.
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    The Nippon Institute of Technology, with Harada Vehicle Design, ZMP, and ZNUG Design, have developed a humanoid robot about the size of an elementary school student for educational purposes.  The university adopted 35 of ZMP's e-nuvo WALK robots in 2004 for a 1:1 student-robot ratio.  Whereas the e-nuvo WALK (the educational version of NUVO) is quite small, the new robot is tall enough to interact with its environment in a more meaningful way.  Students will demonstrate the robot at elementary and junior high schools, as well as care facilities.  The goal is to improve student learning by raising awareness of bipedal robot technology and its connection to math and physics, while also giving them hands-on experience with the bot.  Additionally, by visiting care facilities the university students will come to understand the real-world needs and applications for robots.\nThe e-nuvo HUMANOID stands 126cm (4′) tall and weighs 15kg (33 lbs), with 21 degrees of freedom (2 legs x6, 2 arms x3, head x3), powered by a Lithium Ion battery.  It is equipped with the usual sensors including cameras, accelerometers, gyro sensors, obstacle detection sensors, distance sensors, and peizoelectric sensors, and can be controlled via PC or remote controller.  Besides basic speech capabilities, the robot can serve as a kind of teacher's assistant, since it has a built-in projector which will allow it to display diagrams on a blackboard that might be difficult to explain in words alone.  The robot will be programmed using Microsoft Robotics Developer Studio, which the students have been using to test control algorithms for the e-nuvo WALK robots
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Embedded.com - Early verification cuts design time & cost in algorithm-intensive systems - 1 views

  • Verification of algorithm-intensive systems is a long, costly process. Studies show that the majority of flaws in embedded systems are introduced at the specification stage, but are not detected until late in the development process. These flaws are the dominant cause of project delays and a major contributor to engineering costs. For algorithm-intensive systems —including systems with communications, audio, video, imaging, and navigation functions— these delays and costs are exploding as system complexity increases. It doesn't have to be this way. Many designers of algorithm-intensive systems already have the tools they need to get verification under control. Engineers can use these same tools to build system models that help them find and correct problems earlier in the development process. This can not only reduce verification time, but also improves the performance of their designs. In this article, we'll explain three practical approaches to early verification that make this possible. First, let's examine why the current algorithm verification process is inefficient and error-prone. In a typical workflow, designs start with algorithm developers, who pass the design to hardware and software teams using specification documents.
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Embedded.com - Picking the right system design methodology for your embedded apps: Part 3 - 0 views

  • A product can be of low quality for several reasons, such as it was shoddily manufactured, its components were improperly designed, its architecture was poorly conceived, and the product's requirements were poorly understood. Quality must be designed in. You can't test out enough bugs to deliver a high-quality product. The quality assurance (QA) process is vital for the delivery of a satisfactory system. In this last part in this series, we will concentrate on portions of the methodology particularly aimed at improving the quality of the resulting system. The software testing techniques described earlier in this series constitute one component of quality assurance, but the pursuit of quality extends throughout the design flow. For example, settling on the proper requirements and specification cannot be overlooked as an important determinant of quality. If the system is too difficult to design, it will probably be difficult to keep it working properly.
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IEEE Spectrum: Carbon Nanotubes Enable Pumpless Liquid Cooling System for Computers - 0 views

  • Researchers at Purdue University have developed a new design employing carbon nanotubes and small copper spheres that wicks water passively towards hot electronics that could meet the challenges brought on by increasing frequency speeds in chips. The problem of overheating electronics is well-documented and in the past the issue has been addressed with bigger and bigger fans. But with chip features shrinking below 50 nanometers the fan solution is just not cutting it. The Purdue researchers, led by Suresh V. Garimella, came up with a design that uses water as the coolant liquid and transfers the water to an ultrathin thermal ground plane. The design naturally pushes the water through obviating the need for a pump and through the use of microfluidic design is able to boil the water fully, which allows the wicking away of more heat.
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Tutorial: Improving the transient immunity of your microcontroller-based embedded desig... - 0 views

  • In many instances, the way embedded software is structured and how it interacts with the hardware in a system can have a profound effect on the transient immunity performance of a system. It can be impractical and costly to completely eliminate transients at the hardware level, so the system and software designers should plan for the occasional erroneous signal or power glitch that could cause the software to perform erratically. Erratic actions on the part of the software can be classified into two different categories:
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Opus - Asynchronous Power Efficient DSP Architecture - 0 views

  • Opus is Octasic's high-performing, ultra low-power, asynchronous DSP technology optimized for basestations, video processing and media gateway solutions. Asynchronous designs deliver similar computing performance to synchronous designs, but use less silicon and less power. No clock tree No state-elements Less sensitive to process and temperature variations
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Embedded.com - The multicore SoC - will 2010 be the turning point? - 0 views

  • Predicting trends is difficult even by the most connected industry experts, but one trend that's easy to spot is the widespread acceptance of multicore SoC. This is happening for a number of reasons. First, it's been years since the workstation first adopted the multicore processor architecture to solve such issues as increasing performance and power concerns. While the adoption rate in workstations is now saturated and is fully supported by General Purpose OSs (GPOS), the embedded world is just now looking at ways to adopt multicore architecture. Second, several SoC vendors have been providing multicore solutions including Cavium, Freescale, MIPS, and ARM; but up until now, these solutions have been limited to networking and used for performance enhancements rather than for low power. The rest of the embedded industry has had limited hardware options available as low-power design is a driving factor. While the ARM 11 MPCore was ahead of its time, the Cortex-A9 MPCore design is ready for primetime and is gaining acceptance in the embedded marketplace. As a result, SoC vendors have adopted the Cortex-A9 MPCore hardware as a basis for their next generation designs. Over a year ago, Texas Instruments pre-announced their next-generation OMAP designs in the OMAP 4 with a dual-core Cortex-A9 MPCore, scheduled for production in the second-half of 2010. ST Microsystems has pre-announced their next generation consumer devices which will be based on the Cortex A9 MPCore.
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Power-aware FPGA design (Part 1) - 0 views

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    "UBM Electronics "
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Electrical noise and mitigation - Part 3: Shielding and grounding (cont.), and filterin... - 0 views

  • A shielded transformer is a two-winding transformer, usually delta"star connected and serves the following purposes: Voltage transformation from the distribution voltage to the equipment's utilization voltage. Converting a 3-wire input power to a 4-wire output thereby deriving a separate stable neutral for the power supply wiring going to sensitive equipment. Keeping third and its multiple harmonics away from sensitive equipment by allowing their free circulation in the delta winding. Softening of high-frequency noise from the input side by the natural inductance
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